EE 421L Digital Electronics Laboratory Laboratory Exercise #8 CMOS Logic Gate Design Department of Electrical and Computer Engineering University of Nevada, at Las Vegas Objective: The purpose of this laboratory exercise is to introduce you to CMOS gate circuits. In this lab, you will measure the characteristics of a CMOS inverter, two-input three-transistor CMOS circuit with a high-impedance Z-state, CMOS Schmitt inverter, and CMOS Schmitt inverter with buffered output and feedback. Equipment Usage For this lab the following equipment will be used: CD4007 Transistor Array, MC14049UB Buffer Power supply Multi-meter Breadboard Oscilloscope Function Generator 10X probe Prelab: Include background information on CMOS technology in your pre-lab report. Discuss the advantages of CMOS technology over NMOS and PMOS. Perform PSPICE simulations of ALL THE GIVEN CIRCUITS. Lab Procedure: For the first part of the experiment, construct the following CMOS inverter circuit on your breadboard: Test various combinations for the inputs and observe the output each time. Record your results in a table. Observe the transfer function on the oscilloscope and sketch the graph. Perform the same procedure described above for the following three circuits: Figure (a) shows the circuit to be tested. Figure (b) shows the circuit in a “High Z” status. Verify all states in your lab work, especially the High Z state status. Comment on this state in your lab write up. This is a Schmidt inverter with buffered output and feedback. Show how all three outputs have slightly different characteristics. Note: In this lab for all inverters, be sure and show the hysteresis curve in addition to the characteristics of the digital logic concerns. Results: In the Results portion of your lab report, include all the data recorded from your experimentation. Include sketches of all your graphs. Questions: 1. How do you design a two-input CMOS NOR gate? (Show the schematic in Orcad Capture). 2. How do you design a two-input CMOS NAND gate? (Show the schematic in Orcad Capture). .