Sequential Circuit Design: Part 1 • Design of memory elements – Static latches – Pseudo-static latches – Dynamic latches • Timing parameters • Two-phase clocking • Clocked inverters James Morizio 1 Sequential Logic Φ FFs LOGIC tp,comb Out In 2 s torage mechanis ms • pos itive feedback • charge-bas ed James Morizio 2 Sequencing • Combinational logic – output depends on current inputs • Sequential logic – output depends on current and previous inputs – Requires separating previous, current, future – Called state or tokens – Ex: FSM, pipeline clk clk clk clk in out CL CL CL Finite State Machine Pipeline James Morizio 3 Sequencing Cont. • If tokens moved through pipeline at constant speed, no sequencing elements would be necessary • Ex: fiber-optic cable – Light pulses (tokens) are sent down cable – Next pulse sent before first reaches end of cable – No need for hardware to separate pulses – But dispersion sets min time between pulses • This is called wave pipelining in circuits • In most circuits, dispersion is high – Delay fast tokens so they don’t catch slow ones. James Morizio 4 Sequencing Overhead • Use flip-flops to delay fast tokens so they move through exactly one stage each cycle. • Inevitably adds some delay to the slow tokens • Makes circuit slower than just the logic delay – Called sequencing overhead • Some people call this clocking overhead – But it applies to asynchronous circuits too – Inevitable side effect of maintaining sequence James Morizio 5 Sequencing Elements • Latch: Level sensitive – a.k.a. transparent latch, D latch • Flip-flop: edge triggered – A.k.a. master-slave flip-flop, D flip-flop, D register • Timing Diagrams clk clk h p c t o D Q D l Q a F – Transparent L – Opaque clk D – Edge-trigger Q (latch) Q (flop) James Morizio 6 Flip-Flop: Timing Definitions Φ t tsetup thold In DATA STABLE t tpFF Out DATA STABLE t James Morizio 7 Maximum Clock Frequency Φ FFs LOGIC tp,comb James Morizio 8 Latch Design • Pass Transistor Latch φ • Pros + Tiny D Q + Low clock load • Cons Used in 1970’s – Vt drop – nonrestoring – backdriving – output noise sensitivity – dynamic – diffusion input James Morizio 9 Latch Design φ • Transmission gate D Q + No Vt drop - Requires inverted clock φ James Morizio 10 Latch Design φ X • Inverting buffer D Q + Restoring φ + No backdriving φ + Fixes either D Q • Output noise sensitivity φ • Or diffusion input – Inverted output James Morizio 11 Latch Design φ • Buffered input X D Q + Fixes diffusion input φ φ + Noninverting φ James Morizio 12 Latch Design φ Q X • Buffered output D + No backdriving φ φ φ • Widely used in standard cells + Very robust (most important) - Rather large - Rather slow (1.5 – 2 FO4 delays) - High clock loading James Morizio 13 Latch Design φ • Tristate feedback X D Q + Static φ – Backdriving risk φ • Static latches are now essential φ James Morizio 14 Latch Design φ Q • Datapath latch X D + Smaller, faster φ φ - unbuffered input φ James Morizio 15 Design of Memory Elements D C C Φ C Φ C Φ Φ Q Q Positive edge-triggered D flip-flop Why use inverters on outputs? Skew Problem : Φ may be delayed with respect to Φ (both may be 1 at the same time) This is what happens- Q D Eliminating/Reducing skew: Q Φin Φ 1 Transmission gate acts a buffer, should have same C Φ delay as inverter James Morizio 16 Latch design C Q D Q D C Φ C Φ Φ Φ Static D latch “Jamb” latch Weak inverter James Morizio 17 Latch Design Variant of D latch C C D Φ Q Φ Φ Φ D Q Φ Φ James Morizio 18 Flip-Flop Design • Flip-flop is built as pair of back-to-back latches φ φ X D Q φ φ φ φ Q X D Q φ φ φ φ φ φ James Morizio 19 Enable • Enable: ignore clock when en = 0 – Mux: increase latch D-Q delay – Clock Gating: increase en setup time, skew Symbol Multiplexer Design Clock Gating Design φ en φ φ h h D 1 h c c c t D t Q t Q D Q a a a L L 0 L en en φ en φ φ D 1 p o l Q 0 F p p o o l D l Q D Q F F en en James Morizio 20 Reset • Force output low when reset asserted • Synchronous vs. asynchronous φ φ S y m h p c b t o l o D Q D Q a F l L reset reset S y n c h φ Q φ φ Q r o n o reset reset u Q s D D R φ φ e φ s φ φ φ e t φ φ φ A Q Q s φ y φ φ n c h reset r reset o D n o D φ u φ φ s φ φ φ R e s e reset t reset φ φ φ James Morizio 21 Set / Reset • Set forces output high when enabled • Flip-flop with asynchronous set and reset φ φ reset set Q D φ φ φ φ set reset φ φ James Morizio 22 Dynamic Latches • So far, all latches have been static-store state when clock is stopped but power is maintained • Dynamic latches reduce transistor count • Eliminate feedback inverter and transmission gate • Latch value stored on the capacitance of the input (gate capacitance) James Morizio 23 Dynamic Latch and Flip-Flop D C Q C Dynamic D latch Data stored as Φ Charge on gate capacitance D C C Q Dynamic negative edge-triggered D Φ flip-flop Φ • Difficult to ensure reliable operation • Similar to DRAM • Refresh cycles are required James Morizio 24 Charge-Based Storage Q Φ D Q Φ Non-overlapping clocks Schematic diagram P s e udo -s tatic Latc h James Morizio 25 Master-Slave Flip-Flop Φ Φ Q A D B Φ Φ To reduce skew: generate complement of clock within the cell Extra inverter per cell Overlapping Clocks Can Caus e • Race Conditions • Undefined Signals James Morizio 26 Two-Phase Clocking • Inverting a single clock can lead to skew problems • Employ two non-overlapping clocks for master and slave sections of a flip-flop • Also, use two phases for alternating pipeline stages James Morizio 27 Two-Phase Clocking Φ 1 D C C Q Φ 2 Φ 1 Φ2 Φ1(t) . Φ2(t) = 0 Φ1=1, Φ2 = 0 D Q Φ1=0, Φ2 = 1 D Q James Morizio 28 2-phase non-overlapping clocks Φ Pseudo-static Φ1 2 Q D flip-flop D Φ2 Φ1 Φ1 Important: Φ2 Non-overlap time t must be kept small t James Morizio 29 2-phase dynamic flip-flop φ1 φ2 D Q Input Sampled φ1 φ2 Output Enable James Morizio 30 Use of “p” Leakers Φ1 Φ2 No need to route Flip-flop D Q Φ signals based on nMOS pass gates Degraded voltage VDD-Vt Φ1 Φ2 D Q pMOS leaker transistors provide full-restored logic Problem: Increased delay levels (extra inverter) James Morizio 31 Clocked Inverters Φ Similar to tristate buffer Φ = 1, acts as inverter Φ = 0, output = Z Φ Φ Q D i1 i2 i3 Φ D Q Φ D Latch James Morizio 32 Flip-flop insensitive to clock overlap VDD VDD M2 M6 φ M4 φ M8 X In D C C φ M3 L1 φ M7 L2 M1 M5 φ−section φ−section C2MOS flip-flop James Morizio 33 C2MOS avoids Race Conditions VDD VDD VDD VDD M2 M6 M2 M6 0 M4 0 M8 X X In D In D 1 M3 1 M7 M1 M5 M1 M5 (a) (1-1) overlap (b) (0-0) overlap James Morizio 34.