Analysis and Design of Analog Integrated Circuits Lecture 8 Cascode Techniques Michael H. Perrott February 15, 2012 Copyright © 2012 by Michael H. Perrott All rights reserved. M.H. Perrott Review of Large Signal Analysis of Current Mirrors Vdd Δ V2 I I 1 2 1 μ W2 2 λ nCox (VGS2-VTH) (1+ 2Vds2) I2 2 L = 2 I 1 W 2 1 μ C 1(V -V ) (1+λ V ) 2 n ox GS1 TH 1 ds1 M L1 2 ΔV M1 Vds2 > Vdsat2 1 V +ΔV V +ΔV Δ Δ Δ Δ Vss=0 TH 1 TH 2 But, VTH+ V1=VTH+ V2 V1 = V2 λ I2 W2 L1 (1+ 2Vds2) I2 = λ I1 W1 L2 (1+ 1Vds1) M2 in Saturation Current Mismatch setting due to Vds based on difference M2 in Triode geometry Note: for accurate ratio, set L1 = L2 Vds2 Vdsat2 M.H. Perrott 2 The Issue of Vds Mismatch in Current Mirrors V λ dd I2 W2 (1+ 2Vds2) = λ I1 W1 (1+ 1Vds1) I1 I2 Current Mismatch setting due to Vds based on difference geometry V V ds1 ds2 Note: we are assuming L = L M1 M2 1 2 . Issue: Current I2 can vary significantly as a function of the drain voltage of M2 - We often want a tightly controlled current set only by I1 and transistor sizes . How do we improve the current mirror matching performance? M.H. Perrott 3 Cascoded Current Source I Rth R ref d3 thd3 Ibias Vbias V M bias 3 M3 M ro1 2 M1 . Offers increased output resistance - Reduces small signal dependence of output current on the output voltage of the current source - From Lecture 6, we derived: . Output resistance boosted by intrinsic gain of M3, gm3ro3 . But how do we reduce the influence of large signal Vds mismatch between M1 and M2? M.H. Perrott 4 Match Vds of Current Mirror Devices With Proper Bias Vdd I1 I2 λ I2 W1 L4 (1+ 1Vds1) Recall: = V I1 W L (1+λ V ) M3 M2 o 4 1 4 ds4 V > ΔV W/L W/L ds2 Current Mismatch Δ Δ VTH+ V VTH+ V setting due to Vds based on difference M4 M1 geometry Δ W/L W/L Vds1 = VTH+ V V +ΔV V +ΔV Vss=0 TH TH . Key transistor for determining I2 is M1 - Why is M2 less important? . Above biasing approach provides a much closer match between Vds1 and Vds4 W1 1+λVds1 W1 I2 = I1 I1 W4 1+λVds4 ≈ W4 M.H. Perrott 5 The Drawback of Basic Cascode Bias Approach Vdd I2 I 1 M1 and M2 M1 in saturation I2 in saturation M2 in triode V M3 M2 o Δ W/L W/L Vds2 > V M1 and M2 Δ Δ in triode VTH+ V VTH+ V M M V 4 1 V V +2ΔV o Δ 1 TH W/L W/L Vds1 = VTH+ V V +ΔV Δ calculation of V1 is nontrivial Vss=0 TH VTH+ V . Output voltage range is reduced - Now Vo must be > VTH + 2V - What will happen to the output impedance of the current source if the output voltage is too low? - Can we improve the voltage range? M.H. Perrott 6 Improved Swing Cascode I2 M1 and M2 in saturation Vdd M1 and M2 in triode no wasted voltage region I1 Δ 2VTH+3 V Vo I2 Vdsat1+Vdsat2 M3 M5 αW/L W/L Vo V +2ΔV M2 V +2ΔV V +ΔV TH Δ TH TH W/L Vds2 > V Δ VTH+ V M4 M6 M1 W/L W/L V = ΔV W/L ds1 Δ Δ Δ Vss=0 VTH+ V VTH+ V VTH+ V . Key idea: set size of M3 such that Vds1 = V - Assuming strong inversion for M1 and M3: M.H. Perrott 7 Alternative Implementation of Improved Swing Cascode I2 M1 and M2 in saturation Vdd M5 M6 M7 M1 and M2 no wasted voltage region Wp/Lp in triode Wp/Lp Wp/Lp I1 I1 I2 V 2ΔV o Vo M3 M2 Δ αW/L W/L Vds2 > V I1 Δ Δ VTH+2 V VTH+ V M4 M1 Δ W/L W/L Vds1 = V V +ΔV Δ Vss=0 TH VTH+ V . Set as on previous slide . Note: both implementations share a common problem M.H. Perrott 8 The Issue of Current Mismatch I1 I2 V +2ΔV M2 λ TH I2 W2 (1+ 2Vds2) Recall: = I W (1+λ V ) Δ 1 1 1 ds1 VTH+ V Mismatch M4 M1 due to Vds Δ Δ Vds4 = VTH+ V Vds1 = V difference W/L W/L . The improved swing approach causes a systematic mismatch between I2 and I1 - Key issue: Vds1 Vds4 . Can we fix this problem? M.H. Perrott 9 Techniques to Reduce Current Mismatch I1 I2 M3 V +2ΔV M2 W/L TH W/L Δ Δ VTH+ V VTH+ V M4 M1 Δ Δ Vds4 = V Vds1 = V W/L W/L . Systematic mismatch between I1 and I2 is greatly reduced by using the above circuit (now Vds1 ≈ Vds4) - Note that gate bias on M2 and M3 may be provided by previously discussed circuits . Additional techniques for accurately matching I1 and I2 - Set L1 = L4 >> Lmin . Note: set L2 = L3 ≈ Lmin for lower area and capacitance - Set W2/W3 = I2/I1 so that V2 = V3 M.H. Perrott 10 Another Common Cascode Bias Topology Vdd M5 M6 M7 Wp/Lp Wp/Lp Wp/Lp I1 I1 M8 W/L M9 Δ VTH+2 V W/L M10 I2 W/L M 11 M3 M2 W/L W/L W/L I1 M Δ Δ 12 VTH+ V VTH+ V W/L M13 M4 M1 Δ Δ W/L Vds4 = V Vds1 = V W/L W/L . Key issue: needs two bias current branches M.H. Perrott 11 Utilizing a Simple Resistor to Achieve One Bias Branch M5 M7 Wp/Lp Wp/Lp I1 Δ VTH+2 V Δ V RB I2 M3 M2 W/L W/L I1 Δ Δ VTH+ V VTH+ V M4 M1 Δ Δ Vds4 = V Vds1 = V W/L W/L . Issue: poly resistor is large and won’t track NMOS devices across temperature and process variations M.H. Perrott 12 Better Approach: Use PMOS Device In Triode Region M5 M7 Wp/Lp Wp/Lp I1 Δ VTH+2 V M6 Δ Wp/Lp V I2 M3 M2 W/L W/L I1 Δ Δ VTH+ V VTH+ V M4 M1 Δ Δ Vds4 = V Vds1 = V W/L W/L . Much smaller, better tracking with NMOS devices than resistor M.H. Perrott 13 Wilson Current Mirror I2 R I1 thd2 M2 M3 M1 . Relies on feedback in its operation . Using Hybrid- analysis - Output resistance comparable to cascode current source . This circuit is rarely used these days M.H. Perrott 14 Enhanced Cascode Current Source I I bias bias2 Iref M4 M3 M 2 M1 . Offers output resistance comparable to double cascode current source . As with Wilson mirror, analysis is tricky due to source/gate coupling - Using results shown in the following slide: M.H. Perrott 15 Thevenin Resistances for CMOS Transistor Feedback Pair R R R RC A C A R M D thd D Rthd 4 M4 M3 vgs4 gm4vgs4 -gmb4vs4 ro4 S M3 Rths RB S ro3 -gmb3vs3 gm3vgs3 vgs3 Rths vs4 RB vs3=0 M.H. Perrott 16 Basic Cascode Amplifier RD V out M2 M2 R ths2 is2 d2 RG M1 α i v Vin 2 s2 Rth RD out RS d2 s2 M1 Common Gate R RG g1 ths1 is1 d1 vin Rth v Av1vg1 α i R g1 g1 1 s1 thd1 s1 General Model RS . Allows improved frequency response (discussed later) . Reduction to two-port will be done in several steps M.H. Perrott 17 Eliminate Middle Sections RD V out M2 M2 R ths2 is2 d2 RG M1 α i v Vin 2 s2 Rth RD out RS d2 s2 M1 RG g1 d1 vin Rth v G v R g1 g1 m1 g1 thd1 . Calculation of Gm1 same as for common source amp . To reduce further, note that M.H. Perrott 18 Resulting Two-Port Similar to Common Source Amp RD V out M2 M2 d2 RG M1 G v v Vin m1 g1 Rth RD out RS d2 M1 RG g1 v R in thg1 vg1 . Key difference: drain impedance much larger M.H. Perrott 19 Slight Twist to Cascode Amplifier Vdd RL Vout RL Vout Ibias 1 is1 ro1 gm1+gmb1 Vbias Iin is1 M1 i Vin in ro4 ro2 M4 M2 M3 Vss=0 . What is the difference between this amplifier and basic cascode amplifier? . What are the constraints in setting Vbias? . What is the maximum output voltage swing? M.H. Perrott 20 Constraints on Vbias and Output Range Vdd RL Vout Ibias M1 Δ > V1 Vbias Iin Δ VTH+ V1 Δ Δ Vin > V4 > V2 M4 M2 M3 Vss=0 . To keep M2 and M4 in saturation . To keep M1 in saturation M.H. Perrott 21 Calculation of Maximum Output Range Vdd RL Vout Ibias M1 Δ > V1 Vbias Iin Δ VTH+ V1 Δ Δ Vin > V4 > V2 M4 M2 M3 Vss=0 . Minimum Vbias allows the maximum output range . Resulting output range M.H. Perrott 22 Variation on a Theme: Enhanced Cascode Amplifiers Ibias1 Ibias2 R1 Vout M4 Input Source M3 I M in Rs 2 M1 . We can turn the enhanced cascode current source into an amplifier - Inject a current input at the source of M4 . Key aspects of small signal analysis can be done using Thevenin method - Simply leverage Thevenin resistance formulas shown on Slide 16 M.H.