I2A2 Universidad Politécnica de Madrid Embedded Systems Using Quartus and Buildroot for building Embedded Linux Systems (De1‐SOC) V1.9 Mariano Ruiz Antonio Carpeño 2017 Universidad Politécnica de Madrid Special mentions and recognitions. This document contains some paragraphs in chapter 2 and 3 copied and adapted from the document created by Sahand Kashani‐Akhavan and René Beuchat from the École polytechnique fédérale de Lausanne (EPHL) available at https://github.com/sahandKashani/. Page 2 Table of contents 1 INTRODUCTION ........................................................................................................................... 9 1.1 Document Overview ................................................................................................................ 9 1.2 Acronyms ................................................................................................................................ 9 1.3 Bibliography .......................................................................................................................... 10 1.4 Prerequisites .......................................................................................................................... 11 1.4.1 Hardware. ................................................................................................................................ 11 1.4.2 Software ................................................................................................................................... 11 1.4.3 Other recommendations ......................................................................................................... 11 2 CYCLONE V SOC OVERVIEW ........................................................................................................ 13 2.1 Introduction........................................................................................................................... 13 2.2 Introduction to the Cyclone V Hard Processor System ............................................................ 13 2.3 Features of the HPS ............................................................................................................... 14 2.3.1 SDRAM Controller Subsystem .................................................................................................. 16 2.3.2 Support Peripherals ................................................................................................................. 16 2.3.3 Interface Peripherals ................................................................................................................ 16 2.3.4 On‐Chip Memory ..................................................................................................................... 16 2.4 DE1‐SoC: Development board using a Cyclone V .................................................................... 16 Feature 17 FPGA Device ......................................................................................................................................... 17 2.5 HPS‐FPGA Interfaces in Cyclone V .......................................................................................... 20 2.6 HPS Address Map ................................................................................................................... 20 2.6.1 HPS Address Spaces ................................................................................................................. 20 2.6.2 HPS Peripheral Region Address Map ....................................................................................... 22 2.7 HPS Booting and FPGA Configuration (text reproduced partially from [3]) ............................. 24 2.7.1 HPS Boot and FPGA Configuraon Ordering ............................................................................ 24 2.7.2 Zooming In On the HPS Boot Process ...................................................................................... 26 2.8 Using FPGA‐only .................................................................................................................... 27 2.9 Using HPS & FPGA .................................................................................................................. 27 2.9.1 Bare‐metal Application ............................................................................................................ 27 2.9.2 Application over an Operating System (Linux) ........................................................................ 28 3 USING THE CYCLONE V – CREATING AND TESTING A BASIC BSP (BOARD SUPPORT PACKAGE) .... 29 3.1 Goals ..................................................................................................................................... 29 3.2 Project Structure .................................................................................................................... 29 3.3 Quartus Prime Lite 16.0 Setup ................................................................................................ 30 3.4 System Design with Qsys – HPS .............................................................................................. 33 3.4.1 Instantiating the HPS Component ........................................................................................... 33 3.4.2 Adding SYSID peripheral. ......................................................................................................... 40 3.4.3 Adding the JTAG UART interface. ............................................................................................ 41 3.4.4 Assigning the memory map for the peripherals. ..................................................................... 41 3.4.5 Generating the Qsys System .................................................................................................... 41 3.5 Instantiating the Qsys System ................................................................................................ 42 Page 3 3.6 HPS DDR3 Pin assignments .................................................................................................... 46 3.7 Compiling the design. Generation of the sof and rbf file ......................................................... 47 3.8 Testing DE1‐SoC with Linux prebuilt binaries.......................................................................... 47 3.8.1 Preloader Generation .............................................................................................................. 48 3.8.2 Generating the device tree. ..................................................................................................... 52 3.8.3 Creating the u‐boot.scr script. ................................................................................................. 52 3.8.4 Creating the sdcard image ....................................................................................................... 53 3.8.5 Copying the image to the SD Card (Linux Host) ....................................................................... 56 3.8.6 Copying the image to the SD Card (Windows Host) ................................................................ 57 3.8.7 Connecting the DE1‐SoC. ......................................................................................................... 57 4 BUILDING LINUX USING BUILDROOT .......................................................................................... 61 4.1 Starting the VMware .............................................................................................................. 61 4.2 Configuring Buildroot. ............................................................................................................ 66 4.3 Important conclusions about the configuration of Buildroot. ................................................. 70 4.4 Compiling Buildroot. .............................................................................................................. 70 4.5 Buildroot Output. .................................................................................................................. 71 4.6 Re‐create the SDcard. ............................................................................................................ 72 4.7 Basic test your embedded Linux System ................................................................................. 72 4.7.1 Exercise 1: ................................................................................................................................ 72 5 USING INTEGRATED DEVELOPMENT ENVIRONMENT: ECLIPSE/CDT ............................................ 73 5.1 Adding cross‐compiling tools to PATH variable. ...................................................................... 73 5.2 Cross‐Compiling application using Eclipse. ............................................................................. 73 5.3 Automatic debugging using gdb and gdbserver. ..................................................................... 81 6 DESIGNING CUSTOM PERIPHERALS IN THE FPGA. ....................................................................... 83 6.1 Creating an external peripheral connected to HPS parallel I/O: Displays Test. ........................ 83 6.1.1 VHDL Hardware Model. ........................................................................................................... 83 6.1.2 Exercise 2: analyse the code and answer these questions: ..................................................... 85 6.1.3 Adding the “displays_ctrl” parallel IO port to the system. ...................................................... 85 6.1.4 Implementing the