The Pennsylvania State University The Graduate School SOFT ERROR RATE SIMULATION AND INITIAL DESIGN CONSIDERATIONS OF NEUTRON INTERCEPTING SILICON CHIP (NISC) A Dissertation in Nuclear Engineering by Cihangir C¸elik c 2010 Cihangir C¸elik Submitted in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy December 2010 The dissertation of Cihangir C¸elik was reviewed and approved∗ by the following: Kenan Unl¨ u¨ Professor of Mechanical and Nuclear Engineering Department Dissertation Advisor, Chair of Committee Jack S. Brenizer J. “Lee” Everett Professor of Mechanical and Nuclear Engineering Department Kostadin Ivanov Distinguished Professor of Mechanical and Nuclear Engineering Department Arthur T. Motta Professor of Nuclear Engineering and Materials Science and Engineering Chair of the Nuclear Engineering Program Vijaykrishnan Narayanan Professor of Computer Science and Engineering Department Tim Z. Hossain Fellow, Cerium Laboratories Special Member ∗Signatures are on file in the Graduate School. Abstract Advances in microelectronics result in sub-micrometer electronic technologies as pre- dicted by Moore’s Law, 1965, which states the number of transistors in a given space would double every two years. The most available memory architectures today have sub- micrometer transistor dimensions. The International Technology Roadmap for Semi- conductors (ITRS), a continuation of Moore’s Law, predicts that Dynamic Random Ac- cess Memory (DRAM) will have an average half pitch size of 50 nm and Microprocessor Units (MPU) will have an average gate length of 30 nm over the period of 2008-2012. Decreases in the dimensions satisfy the producer and consumer requirements of low power consumption, more data storage for a given space, faster clock speed, and porta- bility of integrated circuits (IC), particularly memories. On the other hand, these prop- erties also lead to a higher susceptibility of IC designs to temperature, magnetic inter- ference, power supply, and environmental noise, and radiation. Radiation can directly or indirectly affect device operation. When a single energetic particle strikes a sensitive node in the micro-electronic device, it can cause a permanent or transient malfunction in the device. This behavior is called a Single Event Effect (SEE). SEEs are mostly transient errors that generate an electric pulse which alters the state of a logic node in the memory device without having a permanent effect on the functionality of the device. This is called a Single Event Upset (SEU) or Soft Error. Contrary to SEU, Single Event Latchup (SEL), Single Event Gate Rapture (SEGR), or Single Event Burnout (SEB) they have permanent effects on the device operation and a system reset or recovery is needed to return to proper operations. The rate at which a device or system encounters soft errors is defined as Soft Error Rate (SER). The semiconductor industry has been struggling with SEEs and is taking necessary measures in order to continue to improve system designs in nano-scale technologies. Prevention of SEEs has been studied and applied in the semiconductor industry by including radiation protection precautions in the system architecture or by using corrective algorithms in the system operation. De- creasing 10B content (20 % of natural boron) in the natural boron of Borophosphosilicate iii glass (BPSG) layers that are conventionally used in the fabrication of semiconductor de- vices was one of the major radiation protection approaches for the system architecture. Neutron interaction in the BPSG layer was the origin of the SEEs because of the 10B (n,α) 7Li reaction products. Both of the particles produced have the capability of ion- ization in the silicon substrate region, whose thickness is comparable to the ranges of these particles. Using the soft error phenomenon in exactly the opposite manner of the semiconduc- tor industry can provide a new neutron detection system based on the SERs in the semi- conductor memories. By investigating the soft error mechanisms in the available semi- conductor memories and enhancing the soft error occurrences in these devices, one can convert all memory using intelligent systems into portable, power efficient, direction- dependent neutron detectors. The Neutron Intercepting Silicon Chip (NISC) project aims to achieve this goal by introducing 10B-enriched BPSG layers to the semiconduc- tor memory architectures. This research addresses the development of a simulation tool, the NISC Soft Error Analysis Tool (NISCSAT), for soft error modeling and analysis in the semiconductor memories to provide basic design considerations for the NISC. NISCSAT performs particle transport and calculates the soft error probabilities, or SER, depending on energy depositions of the particles in a given memory node model of the NISC. Soft error measurements were performed with commercially available, off-the-shelf semiconductor memories and microprocessors to observe soft error variations with the neutron flux and memory supply voltage. Measurement results show that soft errors in the memories increase proportionally with the neutron flux, whereas they decrease with increasing the supply voltages. NISC design considerations include the effects of device scaling, 10B content in the BPSG layer, incoming neutron energy, and critical charge of the node for this dissertation. NISCSAT simulations were performed with various mem- ory node models to account these effects. Device scaling simulations showed that any further increase in the thickness of the BPSG layer beyond 2 µm causes self-shielding of the incoming neutrons due to the BPSG layer and results in lower detection efficien- cies. Moreover, if the BPSG layer is located more than 4 µm apart from the depletion region in the node, there are no soft errors in the node due to the fact that both of the reaction products have lower ranges in the silicon or any possible node layers. Calcu- lation results regarding the critical charge indicated that the mean charge deposition of the reaction products in the sensitive volume of the node is about 15 fC. It is evident that the NISC design should have a memory architecture with a critical charge of 15 fC or less to obtain higher detection efficiencies. Moreover, the sensitive volume should be placed in close proximity to the BPSG layers so that its location would be within the range of α and 7Li particles. Results showed that the distance between the BPSG layer and the sensitive volume should be less than 2 µm to increase the detection efficiency of the NISC. Incoming neutron energy was also investigated by simulations and the re- iv sults obtained from these simulations showed that NISC neutron detection efficiency is related with the neutron cross-sections of 10B (n,α) 7Li reaction, e.g., ratio of the ther- mal (0.0253 eV) to fast (2 MeV) neutron detection efficiencies is approximately equal to 8000:1. Environmental conditions and their effects on the NISC performance were also studied in this research. Cosmic rays were modeled and simulated via NISCSAT to investigate detection reliability of the NISC. Simulation results show that cosmic rays account for less than 2 % of the soft errors for the thermal neutron detection. On the other hand, fast neutron detection by the NISC, which already has a poor efficiency due to the low neutron cross-sections, becomes almost impossible at higher altitudes where the cosmic ray fluxes and their energies are higher. NISCSAT simulations regarding soft error dependency of the NISC for temperature and electromagnetic fields show that there are no significant effects in the NISC detection efficiency. Furthermore, the de- tection efficiency of the NISC decreases with both air humidity and use of moderators since the incoming neutrons scatter away before reaching the memory surface. v Table of Contents List of Figures ix List of Tables xii Acknowledgments xv Chapter 1 Introduction1 1.1 Soft Errors . .2 1.2 Radiation Induced Soft Errors . .4 1.2.1 Cosmic Rays . .5 1.2.2 Alpha Particles . 10 1.2.3 Neutron Induced Boron Reactions . 10 1.2.4 Spontaneous Fission Sources . 14 1.3 Motivation and Statement of Objectives . 16 Chapter 2 Basic Design Considerations 19 2.1 Alternative Semiconductor Materials . 19 2.2 Alternative Chip Designs . 21 2.3 Sample Soft Error Rate Calculation . 24 2.4 Overall NISC Design Approaches . 26 Chapter 3 Soft Error Rate Measurements 28 3.1 Measurement of Memory Soft Error Rates . 28 3.1.1 Experimental Setup . 29 3.1.2 Experimental Results . 29 vi 3.2 Measurement of Microprocessor Soft Error Rates . 30 3.2.1 Experimental Setup . 30 3.2.2 Experimental Results . 32 Chapter 4 NISC Soft Error Analysis Tool (NISCSAT) 35 4.1 Geant4 . 35 4.2 NISCSAT . 38 4.2.1 Geometry . 38 4.2.2 Material, Temperature, and Electromagnetic Field . 39 4.2.3 Physics . 40 4.2.4 Source . 41 4.2.5 Soft Error Probability . 41 4.3 NISC Node Model and NISCSAT Verification . 42 Chapter 5 Soft Error Analysis of the NISC 45 5.1 NISC Simulation Model and Investigation of the Model Parameters . 45 5.1.1 Boron Content in the BPSG Layer . 47 5.1.2 Device Scaling . 50 5.1.3 Critical Charge . 52 5.1.4 Neutron Energy . 54 5.1.5 Array Structure . 58 5.1.6 Sensitive Volume . 63 5.1.7 Intermediate Node Layers . 64 5.2 Directional Neutron Detection Capability of the NISC . 68 5.2.1 Mono-directional Plane Source Calculations . 68 5.2.2 Isotropic Point Source Calculations . 78 5.3 Statistics in the NISC Simulations . 84 Chapter 6 Cosmic Ray Background and Environmental Effects on the NISC 86 6.1 Cosmic Rays . 86 6.1.1 Cosmic Rays Modeling . 87 6.1.2 Simulation Results . 88 6.2 Environmental Effects . 93 6.2.1 Temperature Effects in the NISC Model . 93 6.2.2 Humidity Effects in the NISC Model . 94 6.2.3 Moderator Effects in the NISC Model . 95 vii 6.2.4 Electric and Magnetic Field Effects in the NISC Model .