ExpressLane PEX 8311AA PCI Express-to-Generic Local Bus Bridge Data Book Version 1.0 December 2009 Website www.plxtech.com Technical Support www.plxtech.com/support Phone 800 759-3735 408 774-9060 FAX 408 774-2169 Copyright © 2009 by PLX Technology, Inc. All Rights Reserved – Version 1.0 December, 2009 Data Book PLX Technology, Inc. Copyright Information Copyright © 2005 - 2009 PLX Technology, Inc. All Rights Reserved. The information in this document is proprietary to PLX Technology. No part of this document may be reproduced in any form or by any means or used to make any derivative work (such as translation, transformation, or adaptation) without written permission from PLX Technology. PLX Technology provides this documentation without warranty, term or condition of any kind, either express or implied, including, but not limited to, express and implied warranties of merchantability, fitness for a particular purpose, and non-infringement. While the information contained herein is believed to be accurate, such information is preliminary, and no representations or warranties of accuracy or completeness are made. In no event will PLX Technology be liable for damages arising directly or indirectly from any use of or reliance upon the information contained in this document. PLX Technology may make improvements or changes in the product(s) and/or the program(s) described in this documentation at any time. PLX Technology retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata. PLX Technology assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX Technology products. PLX Technology, the PLX logo, and Data Pipe Architecture are registered trademarks and ExpressLane is a trademark of PLX Technology, Inc. PCI Express is a trademark of the PCI Special Interest Group (PCI-SIG). Tri-State is a registered trademark of National Semiconductor Corporation. All product names are trademarks, registered trademarks, or servicemarks of their respective owners. Document Number: 8311AA-SIL-DB-P1-1.0 ExpressLane PEX 8311AA PCI Express-to-Generic Local Bus Bridge Data Book, Version 1.0 ii Copyright © 2009 by PLX Technology, Inc. All Rights Reserved December, 2009 Revision History Revision History Version Date Description of Changes 1.0 December, 2009 Initial Production Release, Silicon Revision AA. Security category changed. Terms and abbreviations – Local Bus Mode, Tx ant Rx definitions updated. Chapter 1: commercial temperature range details changed Chapter 2: • Local Bus Mode details changed, Tables 2-4, 2-5 • Reference to AL_BTT24_U buffer removed, Table 2-8 • Miscellaneous signals, CLKIN and CLKOUT details added, Table 2-10 • JTAG interface, TRST# details changed, Table 2-11 • Test signal, IDDQEN# resistor value changed, Table 2-12 • No connect pins description changed, Table 2-13 • References to 9054 removed, Section 2.4 Chapter 7: • Timing diagram numbering corrected • Removal of Reset Operaiton and Direct Data Transfer Mode sections Chapter 8: reference to LCS_PCIBAR0 added, section 8.3.2.2 Chapter 9, changes to: • Direct Master Delayed Read Mode section restructured, Section 9.2.6 • Direct Master Read Ahead Mode details changed, Section 9.2.7 • Internal PCI Bus Master/Target Abort details changed, Section 9.2.9 • Direct Master Write FIFO Programmable Almost Full, Section 9.2.11 • IDMA OPeration details changed, Section 9.2.13 • Direct Slave Writes details changed, Section 9.3.1.2 • Direct Slave Delayed Read Mode PCI details added, Seciton 9.3.4.2 • Slave Transfer Error now M mode only, Section 9.3.9 • Figures 9-9 and 9-10 changed order • Replaced DMA Demand Mode, Channel x – C and J Modes, Section 9.5.13.1 • Replaced DMA Demand Mode, Channel x – M Mode, section 9.5.13.2 • Removal of Fast Terminate Mode Operation section • Removal of Slow Terminate Mode Operation section • Removal of End of Transfer Input section Chapter 12: • Figure 12-1 changed • Endpoint Mode Local Interrupts note changed, Section 12.3 Chapter 14: • Endpoint Mode PCI Express-PM Device Power States recovery time detaios changed, Seciton 14.2.4 Chapter 19: • Register 19-25. Offset 24h PECS_PREBASE Prefetchable Memory Base bits 3:0 • Register 19-48. Offset 52h PECS_MSICTL Message Signaled Interrupts Control bit 0 • Register 19-56. Offset 68h PECS_DEVCTL PCI Express Device Control bit 10 • Register 19-89. Offset 1040h PECS_CHIPREV Chip Silicon Revision bits 15:0 • Register 19-92. Offset 104Ch PECS_TLPCFG1 TLP Controller Configuration 1 bits 13:21 Chapter 23: Recommended Operating Conditions, operating temperature note added, Section 23.5 Chapter 24: • PEX 8311 Package Thermal Resistance values changed, Table 24-2 • Mechanical dimensions image changed, Figure 24-1 ExpressLane PEX 8311AA PCI Express-to-Generic Local Bus Bridge Data Book, Version 1.0 Copyright © 2009 by PLX Technology, Inc. All Rights Reserved iii Data Book PLX Technology, Inc. Preface The information contained in this data book is subject to change without notice. This data book will be updated periodically as new information is made available. Scope This data book is the primary source of technical documentation describing the features, functions and operations of the PLX Technology PEX 8311 PCI Express-to-Generic Local Bus Bridge. Intended Audience This data book provides functional details of PLX Technology’s ExpressLane PEX 8311AA PCI Express-to-Generic Local Bus Bridge, for hardware designers and software/firmware engineers. Supplemental Documentation This data book assumes that the reader is familiar with the following documents: • PLX Technology, Inc. (PLX) 870 W Maude Avenue, Sunnyvale, CA 94085 USA Tel: 800 759-3735 (domestic only) or 408 774-9060, Fax: 408 774-2169, www.plxtech.com The PLX PEX 8311 Toolbox includes this data book, as well as other PEX 8311 documentation, including the Errata. • PCI Special Interest Group (PCI-SIG) 3855 SW 153rd Drive, Beaverton, OR 97006 USA Tel: 503 619-0569, Fax: 503 644-6708, www.pcisig.com – PCI Local Bus Specification, Revision 3.0 – PCI Local Bus Specification, Revision 2.2 – PCI Local Bus Specification, Revision 2.1 – PCI to PCI Bridge Architecture Specification, Revision 1.1 – PCI Bus Power Management Interface Specification, Revision 1.1 – PCI Hot Plug Specification, Revision 1.1 – PCI Standard Hot Plug Controller and Subsystem Specification, Revision 1.0 – PCI Express Base Specification, Revision 1.0a – PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0 – PCI Express Card Electromechanical Specification, Revision 1.1 • The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 445 Hoes Lane, Piscataway, NJ 08854-4141 USA Tel: 800 701-4333 (domestic only) or 732 981-0060, Fax: 732 981-9667, www.ieee.org – IEEE Standard 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture, 1990 – IEEE 1149.1a-1993, IEEE Standard Test Access Port and Boundary-Scan Architecture – IEEE Standard 1149.1b-1994, Specifications for Vendor-Specific Extensions ® • I2O Special Interest Group (I2O SIG ) www.developer.osdl.org/dev/opendoc/Online/Local/I20/index.html – Intelligent I/O (I2O) Architecture Specification, Revision 1.5 • Other References – Advanced Configuration and Power Interface (ACPI) Specification, Revision 2.0 ExpressLane PEX 8311AA PCI Express-to-Generic Local Bus Bridge Data Book, Version 1.0 iv Copyright © 2009 by PLX Technology, Inc. All Rights Reserved December, 2009 Supplemental Documentation Abbreviations Supplemental Documentation Abbreviations Note: In this data book, shortened titles are provided to the previously listed documents. The following table defines these abbreviations. Abbreviation Document PCI r3.0 PCI Local Bus Specification, Revision 3.0 PCI r2.2 PCI Local Bus Specification, Revision 2.2 PCI r2.1 PCI Local Bus Specification, Revision 2.1 PCI-to-PCI Bridge r1.1 PCI to PCI Bridge Architecture Specification, Revision 1.1 PCI Power Mgmt. r1.1 PCI Bus Power Management Interface Specification, Revision 1.1 PCI Hot Plug r1.1 PCI Hot Plug Specification, Revision 1.1 PCI Standard Hot Plug Controller and Subsystem Specification, PCI Standard Hot Plug r1.0 Revision 1.0 PCI Express Base 1.0a PCI Express Base Specification, Revision 1.0a PCI Express-to-PCI/ PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0 PCI-X Bridge r1.0 PCI Express CEM 1.1 PCI Express Card Electromechanical Specification, Revision 1.1 I2O r1.5 Intelligent I/O (I2O) Architecture Specification, Revision 1.5 IEEE Standard 1149.1-1990 IEEE Standard Test Access Port and Boundary-Scan Architecture Data Assignment Conventions Data Width PEX 8311 Convention Half byte (4 bits) Nibble 1 byte (8 bits) Byte 2 bytes (16 bits) Word 4 bytes (32 bits) DWORD/DWord/Dword 8 bytes (64 bits) QWORD/QWord/Qword ExpressLane PEX 8311AA PCI Express-to-Generic Local Bus Bridge Data Book, Version 1.0 Copyright © 2009 by PLX Technology, Inc. All Rights Reserved v Data Book PLX Technology, Inc. Terms and Abbreviations The following table provides common terms and abbreviations used in this data book. Terms and abbreviations defined in the PCI Express r1.0a are not included in this table. Terms and Definition Abbreviations # Indicates an Active-Low signal. Acknowledge Control Packet. A control packet used by a destination to ACK acknowledge data packet receipt. A signal that acknowledges the signal receipt. ADB Allowable Disconnect Boundary. Asynchronous Inputs and Outputs can be asynchronous to a clock. Level-sensitive signals. BAR Base Address Register. CA Completion with Completer Abort status. Access initiated by PCI Express Configuration transactions on the primary CFG interface. Clock cycle One period of the clock. Completer Device addressed by a Requester. CRS Configuration Retry Status. Configuration Status register; Control and Status register; Command and Status CSR register. Dual Address cycle. A PCI Express transaction wherein a 64-bit address is DAC transferred across a 32-bit data path in two Clock cycles.