, \ EK-OMF32-TO-OO 1 DMF32 Multi-Function Communications . Interface . Technical Description \ . " ~ , EK DMF32 TD 2 EK-DMF32-TD-OO 1 DMF32 Multi-Function Communications Interface Technical Description Prepared by Educational Services of Digital Equipment Corporation Copyright © 1983 by Digital Equipment Corporation All Rights Reserved The information in this document is subject to change without notice and should not be construed as a commitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for any errors that may appear in this document. Printed in U.S.A. The manuscript for this book was created on a DIGITAL Word Processing System and, via a translation program, was automatically typeset on DIGITAL's DECset Integrated Publishing System. Book production was done by Educational Services Development and Publishing in South Lawrence, MA. The following are trademarks of Digital Equipment Corporation: ~DmDD~D DECtape Rainbow DATATRIEVE DECUS RSTS DEC DECwriter RSX DEC mate DIBOL UNIBUS DECnet MASSBUS VAX DECset PDP VMS DECsystem-lO PjOS VT DECSYSTEM-20 Professional Work Processor CONTENTS CHAPTER 1 INTRODUCTION Page 1.1 SCOPE ................................................................................................................ 1-1 1.2 DMF32 DOCUMENTATION .............................................................................. 1-1 1.3 PHYSICAL DESCRIPTION ................................................................................ 1-2 1.4 FUNCTIONAL DESCRIPTION ......................................................................... 1-3 1.4.1 Asynchronous Multiplexer ............................................................................. 1-3 1.4.2 Synchronous Interface ................................................................................... 1-4 1.4.3 Line Print Controller ..................................................................................... 1-4 1.4.4 Parallel Interface ........................................................................................... 1-4 1.5 POWER-UP SELF TEST ..................................................................................... 1-4 1.6 CONTROL STATUS REGISTER (CSR) AND VECTOR ASSIGNMENTS ........ 1-5 1.6.1 DMF32 CSR 0 .............................................................................................. 1-6 1.6.2 DMF32 CSR 1.............................................................................................. 1-8 1.7 POWER SUPPLY REQUIREMENTS ................................................................. 1-8 CHAPTER 2 DMF32 HARDWARE OVERVIEW 2.1 INTRODUCTION ............................................................................................... 2-1 2.2 DMF32 MAJOR COMPONENTS ....................................................................... 2-2 2.3 MICROWORD .................................................................................................... 2-8 CHAPTER 3 DETAILED DESCRIPTION 3.1 INTRODUCTION ............................................................................................... 3-1 3.1.1 UNIBUS Interface ........................................................................................ 3-1 3.1.2 DMF32 Intelligence ....................................................................................... 3-2 3.1.3 Local Store ................................................................................................... 3-3 3.1.4 Internal Bus .................................................................................................. 3-5 3.1.5 Slow Bus ....................................................................................................... 3-5 3.2 UNIBUS Master Control Logic ............................................................................. 3-6 3.2.1 Master Device Pre-Cycle Initiation ................................................................. 3-6 3.2.2 Master Device DATO(B) Cycle .................................................................... 3-11 3.2.3 DMF32 Master Device DATI(P) Cycle ........................................................ 3-13 3.3 UNIBUS INTERRUPT LOGIC ...................................................................... 3-13 3.4 UNIBUS SLAVE I/O OPERATION .................................................................. 3-18 3.4.1 Slave Device Addressing .............................................................................. 3-18 3.4.2 Slave DATO(B) Cycle ................................................................................. 3-20 3.4.3 Slave DATI Cycle ....................................................................................... 3-20 3.4.4 Slave DATIP Cycle .................................................................................. 3-22 3.5 TRAP LOGIC .................................................................................................... 3-22 3.5.1 Trap Control ............................................................................................... 3-22 3.5.2 Trap Addresses ........................................................................................... 3-23 3.5.3 The Trap Routine ........................................................................................ 3-23 3.6 MICROSEQUENCE LOGIC .......................................................................... 3-26 3.6.1 Microsequence Control .............................., .................................................. 3-26 3.6.2 Address Source Selection ............................................................................. 3-30 3.7 CONTROL STORE AND PARITY LOGIC ....................................................... 3-31 3.8 MASTER CLOCK .............................................................................................. 3-31 iii 3.9 ARITHMETIC AND LOGICAL UNIT ........................................................... 3-34 3.9.1 ALU Functions ........................................................................................... 3-35 3.9.2 Shift Control ............................................................................................... 3-35 3.9.3 RAM and A/B Latches ............................................................................... 3-37 3.9.4 ALU Source Operands ................................................................................ 3-37 3.9.5 Source Operand Selection ......................................................................... 3-37 3.9.6 ALU Destination ......................................................................................... 3-38 3.9.7 Condition Codes .......................................................................................... 3-38 3.10 LOCAL STORE CONTROL .............................................................................. 3-39 3.10.1 Local Store Write ........................................................................................ 3-39 3.10.2 Local Store Read ...................................................................................... 3-39 3.10.3 Local Store Addressing ................................................................................ 3-39 3.10.4 Special Local Store Read Instructions ........................................................... 3-39 3.11 REGULAR DISCRETE EXTERNAL REGISTERS READ/WRITE CyCLES ............................................................................... 3-42 3.11.1 Regular Discrete External Register Read ...................................................... 3-42 3.11.2 Regular Discrete External Register Write ..................................................... 3-48 3.12 SLOW READ/WRITE CYCLES .................................................................... 3-52 3.13 SLOW READ/WRITE CONTROL LOGIC ....................................................... 3-52 3.14 SLOW READ AND WRITE STATES ............................................................... 3-57 3.15 EIA/CCITT DRIVERS AND RECEIVERS ....................................................... 3-59 3.16 DR/LP DRIVERS AND RECEIVERS .............................................................. 3-59 3.16.1 DR/LP TTL Drivers ................................................................................ 3-59 3.16.2 DR/LP TTL Receivers ................................................................................ 3-59 FIGURES Figure No. Title Page 1-1 DMF32 Components ......................................................................................... 1-2 1-2 CRS Address Map ............................................................................................ 1-5 2-1 DMF32 Hardware Overview .............................................................................. 2-4 2-2 Microword Bit Fields ......................................................................................... 2-9 3-1 DMF32 Overview ............................................................................................. 3-2 3-2 UNIBUS Master Control Logic ......................................................................... 3-9 3-3 Master Control FSM Flow ............................................................................... 3-10 3-4 UNIBUS Interrupt Logic ................................................................................. 3-14 3-5 Interrupt Control FSM Flow ............................................................................ 3-15 3-6 UNIBUS Slave Control Logic ....................................................................... 3-17 3-7 Slave Control FSM Flow .................................................................................