56255 Rev 3.03 - July, 2018 OSRR for AMD Family 17h processors, Models 00h-2Fh Open-Source Register Reference For AMD Family 17h Processors Models 00h-2Fh 1 56255 Rev 3.03 - July, 2018 OSRR for AMD Family 17h processors, Models 00h-2Fh Legal Notices © 2017,2018 Advanced Micro Devices, Inc. All rights reserved. The information contained herein is for informational purposes only, and is subject to change without notice. While every precaution has been taken in the preparation of this document, it may contain technical inaccuracies, omissions and typographical errors, and AMD is under no obligation to update or otherwise correct this information. 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FIDDLERS GREEN CIRCLE, SUITE 400E, GREENWOOD VILLAGE, COLORADO 80111. 2 56255 Rev 3.03 - July, 2018 OSRR for AMD Family 17h processors, Models 00h-2Fh List of Chapters 1 Open Source Register Reference 2 Core Complex (CCX) 3 Machine Check Architecture 4 SMU Registers 5 Advanced Platform Management Link (APML) 6 SB Temperature Sensor Interface (SB-TSI) List of Namespaces List of Definitions Memory Map - MSR Memory Map - SMN 3 56255 Rev 3.03 - July, 2018 OSRR for AMD Family 17h processors, Models 00h-2Fh Table of Contents 1 Open Source Register Reference 1.1 Intended Audience 1.2 Reference Documents 1.2.1 Documentation Conventions 1.3 Conventions 1.3.1 Numbering 1.3.2 Arithmetic And Logical Operators 1.3.2.1 Operator Precedence and Associativity 1.3.3 Register Mnemonics 1.3.3.1 Logical Mnemonic 1.3.3.2 Physical Mnemonic 1.3.4 Register Format 1.3.4.1 A Register is a group of Register Instances 1.3.4.2 Register Physical Mnemonic, Title, and Name 1.3.4.3 Full Width Register Attributes 1.3.4.4 Register Description 1.3.4.5 Register Instance Table 1.3.4.5.1 Content Ordering in a Row 1.3.4.5.2 Multiple Instances Per Row 1.3.4.5.3 MSR Access Method 1.3.4.5.3.1 MSR Per-Thread Example 1.3.4.5.3.2 MSR Range Example 1.3.4.5.4 BAR Access Method 1.3.4.5.4.1 BAR as a Register Reference 1.3.4.5.5 PCICFG Access Method 1.3.4.5.5.1 PCICFG Bus Implied to be 00h 1.3.4.5.6 Data Port Access Method 1.3.4.6 Register Field Format 1.3.4.7 Simple Register Field Format 1.3.4.8 Complex Register Field Format 1.3.4.9 Field Name is Reserved 1.3.4.10 Field Access Type 1.3.4.10.1 Conditional Access Type Expression 1.3.4.11 Field Reset 1.3.4.12 Field Initialization 1.3.4.13 Field Check 1.3.4.14 Field Valid Values 2 Core Complex (CCX) 2.1 Processor x86 Core 2.1.1 Secure Virtual Machine Mode (SVM) 2.1.1.1 BIOS support for SVM Disable 2.1.1.1.1 Enable AMD Virtualization™ 2.1.1.1.2 Disable AMD Virtualization™ 2.1.1.1.3 Disable AMD Virtualization™, with a user supplied key 2.1.2 Effective Frequency 2.1.3 Address Space 2.1.3.1 Virtual Address Space 2.1.3.2 Physical Address Space 2.1.3.3 System Address Map 2.1.3.3.1 Memory Access to the Physical Address Space 4 56255 Rev 3.03 - July, 2018 OSRR for AMD Family 17h processors, Models 00h-2Fh 2.1.3.3.1.1 Determining Memory Type 2.1.4 Configuration Space 2.1.4.1 MMIO Configuration Coding Requirements 2.1.4.2 MMIO Configuration Ordering 2.1.4.3 Processor Configuration Space 2.1.5 PCI Configuration Legacy Access 2.1.6 Register Sharing 2.1.7 Timers 2.1.8 Interrupts 2.1.8.1 System Management Mode (SMM) 2.1.8.1.1 SMM Overview 2.1.8.1.2 Mode and Default Register Values 2.1.8.1.3 SMI Sources And Delivery 2.1.8.1.4 SMM Initial State 2.1.8.1.5 SMM Save State 2.1.8.1.6 System Management State 2.1.8.1.7 Exceptions and Interrupts in SMM 2.1.8.1.8 The Protected ASeg and TSeg Areas 2.1.8.1.9 SMM Special Cycles 2.1.8.1.10 Locking SMM 2.1.8.2 Local APIC 2.1.8.2.1 Local APIC Functional Description 2.1.8.2.1.1 Detecting and Enabling 2.1.8.2.1.2 APIC Register Space 2.1.8.2.1.3 ApicId Enumeration Requirements 2.1.8.2.1.4 Physical Destination Mode 2.1.8.2.1.5 Logical Destination Mode 2.1.8.2.1.6 Interrupt Delivery 2.1.8.2.1.7 Vectored Interrupt Handling 2.1.8.2.1.8 Interrupt Masking 2.1.8.2.1.9 Spurious Interrupts 2.1.8.2.1.10 Spurious Interrupts Caused by Timer Tick Interrupt 2.1.8.2.1.11 Lowest-Priority Interrupt Arbitration 2.1.8.2.1.12 Inter-Processor Interrupts 2.1.8.2.1.13 APIC Timer Operation 2.1.8.2.1.14 Generalized Local Vector Table 2.1.8.2.1.15 State at Reset 2.1.8.2.2 Local APIC Registers 2.1.9 CPUID Instruction 2.1.9.1 CPUID Instruction Functions 2.1.10 MSR Registers 2.1.10.1 MSRs - MSR0000_xxxx 2.1.10.2 MSRs - MSRC000_0xxx 2.1.10.2.1 MSRs - MSRC000_2xxx 2.1.10.3 MSRs - MSRC001_0xxx 2.1.10.4 MSRs - MSRC001_1xxx 2.1.11 Performance Monitor Counters 2.1.11.1 RDPMC Assignments 2.1.11.2 Large Increment per Cycle Events 2.1.11.3 Core Performance Monitor Counters 2.1.11.3.1 Floating Point (FP) Events 2.1.11.3.2 LS Events 2.1.11.3.3 IC and BP Events 5 56255 Rev 3.03 - July, 2018 OSRR for AMD Family 17h processors, Models 00h-2Fh 2.1.11.3.4 DE Events 2.1.11.3.5 EX (SC) Events 2.1.11.3.6 L2 Cache Events. 2.1.11.4 L3 Cache Performance Monitor Counters 2.1.11.4.1 L3 Cache PMC Events 2.1.12 Instruction Based Sampling (IBS) 3 Machine Check Architecture 3.1 Overview 3.2 Machine Check Architecture Extensions 3.3 Machine Check Global Registers 3.4 Machine Check Banks 3.5 Machine Check Bank Registers 3.6 Legacy MCA MSRs 3.7 Determining Bank Type 3.8 Machine Check Errors 3.9 Machine Check Initialization 3.9.1 Initialization Sequence 3.9.2 Configuration Requirements 3.10 MCA Overflow Recovery 3.11 MCA Recovery 3.12 Use of MCA Information 3.12.1 Error Management 3.12.2 Fault Management 3.13 Machine Check Error Handling 3.14 Error Codes 3.15 Error Thresholding 3.16 Error Simulation 3.17 MCA Registers 3.17.1 Decoding Error Type 3.17.2 Mapping of Banks to Blocks 3.17.3 Hardware IDs and McaType 3.17.4 MCA Banks 3.17.5 LS 3.17.6 IF 3.17.7 L2 3.17.8 DE 3.17.9 EX 3.17.10 FP 3.17.11 L3 Cache 3.17.12 CS 3.17.13 PIE 3.17.14 UMC 3.17.15 Parameter Block 4 SMU Registers 4.1 MP0 Configuration Unit Registers 4.2 Thermal (THM) 4.2.1 Registers 5 Advanced Platform Management Link (APML) 5.1 Overview 5.1.1 Definitions 5.2 SBI Bus Characteristics 5.2.1 SMBus Protocol Support 5.2.2 I2C Support 6 56255 Rev 3.03 - July, 2018 OSRR for AMD Family 17h processors, Models 00h-2Fh 5.3 SBI Processor Information 5.3.1 SBI Processor Pins 5.3.1.1 Physical Layer Characteristics 5.3.2 Processor States 5.4 SBI Protocols 5.4.1 SBI Modified Block Write-Block Read Process Call 5.4.2 SBI Error Detection and Recovery 5.4.2.1 Error Detection 5.4.2.1.1 ACK/NAK Mechanism 5.4.2.1.2 Bus Timeouts 5.4.2.2 Error Recovery 5.4.2.2.1 SBI Bus Reset 5.5 SBI Physical Interface 5.5.1 SBI SMBus Address 5.5.2 SBI Bus Timing 5.5.3 SBI Bus Electrical Parameters 5.5.4 Pass-FET Option 6 SB Temperature Sensor Interface (SB-TSI) 6.1 Overview 6.1.1 Definitions 6.2 SB-TSI Protocol 6.2.1 SB-TSI Send/Receive Byte Protocol 6.2.1.1 SB-TSI Address Pointer 6.2.2 SB-TSI Read/Write Byte Protocol 6.2.3 Alert Behavior 6.2.4 Atomic Read Mechanism 6.2.5 SB-TSI Temperature and Threshold Encodings 6.2.6 SB-TSI Temperature Offset Encoding 6.3 SB-TSI Physical Interface 6.3.1 SB-TSI SMBus Address 6.3.2 SB-TSI Bus Timing 6.3.3 SB-TSI Bus Electrical Parameters 6.3.4 Pass-FET Option 6.4 SB-TSI Registers 7 56255 Rev 3.03 - July, 2018 OSRR for AMD Family 17h processors, Models 00h-2Fh List of Figures Figure 1: Register Physical Mnemonic, Title, and Name Figure 2: Full Width Register Attributes Figure 3: Register Description Figure 4: Register Instance Table: Content Ordering in a Row Figure 5: Register Instance Table: MSR Example Figure 6: Register Instance Table: MSR Range Example Figure 7: Register Instance Table: BAR as Register Reference Figure 8: Register Instance Table: Bus Implied to be 00h Figure 9: Register Instance Table: Data Port Select Figure 10: Simple Register Field Example Figure 11: Register Field Sub-Row for {Reset,AccessType,Init,Check} Figure 12: Register Field Sub-Row for Description Figure 13: Register Field Sub-Row for Valid Value Table Figure 14: Register Field Sub-Row for Valid Bit Table Figure 15: Register Sharing Domains Figure 16: Instance Parameters