Design and Behavior of TSS/ 8: a PDP-8 Based Time-sharing System _U) VhvDE GOOR, STUDENT mm~~,IEEE, C. GORDON BELL, ~EJIBER, IEEE, rn DONALD A. WITCIWFT dbstra::-TSS/8 is an existence proof for a small-scale tin.;- time-sharing system, but with an order of magnitude syxem. Design, development, and performance analysis decrease in the per console cost. &re occurred in quasiparallel. Performance analysis includes two The design was predicated on giving a user a very =c.Cels an2 rxo levels of simulation (using SIMULA). The final simu- kfon, an ticurate model of the real operating system, predicts the short response to a typelvriter or teletype input; but cbsened beharior. the user would have little arithmetic computing capa- bility. Thus, through specialization the systern would Index Tzrnts--Disk, PDP-8 computer, performance analysis, .--dub,-. s;k-ixion, text editing, time-sharing. be used as follows. 1) A preprocessor to larger, rnore general purpose systems. In this mode all trivial tasks (syntax S >I.\\-, 1967 Carnegie-JIellon University began checking, editing, etc.) would be handled by the design of a small-scale time-sharing system. TSS/8, in effect, at the lowcst (cheapest) organi- IThe prixlcipal design goal was a general purpose zational level. Sinlplc computational tasks (e.g., short BASIC programs) \voultl also be run at the \laccx<?: received June 9, 1969; revised July 7, 1969. This periphery. -.-.:-e: .-. w.15 :rexc.nted at the 1969 IEEE Computer Croup Conference, 2) Stand alone general purpose systern. Users not !.l:znc.~y.:~.\linn., June 17-19, 1969. This work was supported by 1 --i-e .-\.dv.\r.=:.d Fesearch Projects ;\gency of the Otlice of the Secretary requiring significant arithmetic capability and :i- -Ocier.;i. ,.F 44620-67-COOS) and is monitored by the Air Force large primary nlenlory wo~~ldusc the system "as -JT.S= ~i %ie::itic Research. .\. \-3.z tte Goor and C. C. Bell are with the Department of is" (e.g., secondary schools and novice program- ,Z - .-q..........-..- S::cnce, C;~r~~rgie-.\I~llonUniversity, Pittsburgh, ['a. ~wrs). :\ \? .::idt was with the DiKital Eqilipllw~~t Curp., hlayl~;ird, :.!sw. He 1s naw with Loyi-Call Systems, Inc., Palo !\lto, Calif. 3) The Insis for dcvcloping spcci;~lizcd systerns. VAN DE GO011 pt 111.: DESIGN ASD IlEIIAVJOR OF TSS/8 Specialized time sharing systems use the basic framework for terminal and file nlanagement (e.g., text editing, hotel reservations, etc.). The main coristrai~ltof the system is based on the PDP-8. The I'DP-8 was selected because of the follow- Though very fast, it represents about the smallest I U(primary; core memory; 4096 vords; 12 bita/vord; 1.5 irs,'wrl: existing computer; any work done using it is easily a P(arithmetic, central; laddress/instruction; 1 2 wrds!lrtrrzxtin) extendable to larger systems. H(secoodary; magnetic tape; - 3 X lo6 bits; 33 rs/wrd) The small primary memory of 4096 words (a "(secondary; fixed head disk; -. S pl/v; taccess: 0 - 34 ms; memory field) has historically restricted the pro- ,1.1 x lo6 vords) gram size; therefore conlplete program swapping rates between primary and secondary memories are quite high. Fig. 1. PDP-8 hardware configuration. PDP-S computers have existed for a long time. The hardware as well as most of the software is well debugged. A slightly larger computer tends to perform A block diagram of the hardware configuration is marginally better for compute-bound1 jobs. (All given in Fig. 1. The PDP-8 is a small, general purpose systems without hardware floating point arith- computer. In its standard configuration it has a core metic appear to have this problem.) For non-com- memory of 4096 (12-bit) words with a 1.5,~sc>-cle time. pute-bound jobs a slightly larger computer tends The memory is expandable in increments of 4096 n-ords to be more swap-bound2 because: (called fields) to a maximum size of eight fields. a) more bits have to be transferred because of the The S(P-M), a processor-memory switch, allom-s the bigger words, processor or the DiVlOl switch to have access to the b) software for these machines tends to be bigger primary memory fields. The S(DbIO1) s~\-ircI~al!on-s (typically SI< words) for about the same func- the high-speed secondary memory, two tape unk= arid tion. a disk, to access primary memory. I 5) A PDP-8 computer was available. The low-speed devices are connected via the S(1,'O) bus. Data transfers to and from these devices is on a The constraints on the design of TSS/8 were the folloiv- character-by-character basis under programmed con- ing. trol. 1) Achieve an order of magnitude improvement in the cost/performance ratio over completely gen- eral purpose time-sharing systems (e.g., 360/67, ~ecauskuser programs written in machice language PDP-10.) are allowed, an effective memory protection schen:c had 2) The system should be able to support about 20 on to be implemented. The instruction set for the PDP-S line users. makes addressing inside a 4096-word memo? heId easy. 3) Response time for jobs with low computational Crossing field boundaries either for data or instructions requirements (like editing) should be good. is relatively difficult, however, because it has to be doile 4) The systenl should be open-ended, i.e., addition by special change data and instruction field insmcrions of future software should be easy. (CDF and ChF) which are in the input-output transfer 5) Existing user programs and system software (like (IOT) class. A simple memory protection scheme is 05- the EDITOR, FORTRAS COMPILER,etc.) should be tained by only allowing a user to access data within a able to run on TSS/8 with no or only minor single field. Any accesses outside the field cause a pio- changes. This would prevent the necessity of re- gram trap. progran~mingthe PDP-8 software. 6) PDP-S hard\vare changes should be kept low such that it \vould be relatively easy to change existing When running programs in a time-s!lared environ- PDP-8 processors. ment, not all instructions from a user program can be 7) The s~~stenlshould be general purpose by provid- executed directly. Some have to be analyzed by the ing protection among the users on a device, core monitor for possible memory protection violation, de- n~emory,and file basis. vice assignment, etc. Hardware was added to allow for this, giving the processor two modes of operation. 1 A job is considered conlpute-bound when it does not terminate the allotted quanta of time running. 1) MONITOR nzode: In this mode all instructions are A system is considered to be swap-bound when the processor is idle and waiting for jobs to be brought from secondary memory into legal and will be executed by the hardware primary memory. directly. 1040 IEEE TRANSACTIONS ON COI\IPUTERS, NOVEMBER 1969 2) USER mode: User programs are run in this mode. continuous address space of the computer into a seg- Certain instructions and classes of instructions are mented BCD-addressed address space of the disk; has illegal here because of their interference with the a buffering system which can be generalized to arbitrary /' time-shared operation. The ilIega3 instructions are: long waiting delays; and has hardware to detect out of HLT halt range disk address requests and to detect and prevent the execution of erroneous commands. The average OSR inclusive OR switch register with AC IOT all input-output transfer instructions. access time is 17.3 ms, the transfer rate is 1 word per 5.0 ps, and the capacity is 1.1 X lo6words. \\'hen any of the illegal instructions occur, a flip-flop Magnetic Tape Memory: At least two magnetic tape is set which when the interrupt is enabled will cause a units are connected to the system. \Vhen TSS/8 is used trap. This n-ill automatically tranfer control to location as a "stand alone" time-sharing system, they are used as 1 of memory field 0 and puts the system in monitor mode "backup" for the disk and as the "mass storagen device (field 0 is the field where the monitor resides) thus trans- for users to enter their files onto the disk. ferring control from the user's program to the monitor. Instructiocs were added and some were changed to USER MACHINE manipulate the mode and trap flip-flops 'and to save Looking at Fig. 2, several levels of machines can be or restore the mode of operation upon entering or exit- identified. The absolute machine is the collection of the ing an interrupt state. TSS/8 hardware components. By adding the monitor to the system, the virtual machine is obtained, which allows time-sharing and adds a set of powerful software- Basicall). the memory is divided into two classes: interpreted instructions. Adding the library programs 1) primary (core) memory (M,) for programs being (e.g., the EDITOR, the FORTRAN COMPILER, BASIC)Creates executed by the processor; the user machine. This is the machine the user sees from 2) secondary memory (M,) for programs which are his console. The user in turn, by writing programs, can not currently active or that are waiting to be create new machines. executed and data files. Instructions to the virtual rnachine allow a user's Primary Jfemmy program to transfer files. In this way a user can have programs of almost arbitrary size which he can cdhtrol The primary memory is a standard core-memory, as a paging environment.