Preliminary Information AMD-K6-2® Processor Data Sheet © 2000 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in AMD's Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. 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The TAP State Diagram is reprinted from IEEE Std 1149.1-1990 “IEEE Standard Test Access Port and Bound- ary-Scan Architecture,” Copyright © 1990 by the Institute of Electrical and Electronics Engineers, Inc. The IEEE disclaims any responsibility or liability resulting from the placement and use in the described manner. Information is reprinted with the permission of the IEEE. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Preliminary Information 21850J/0—February 2000 AMD-K6®-2 Processor Data Sheet Contents Revision Historyxix 1 AMD-K6®-2 Processor . 1 1.1 Super7™ Platform Initiative . 3 Super7™ Platform Enhancements. 3 Super7™ Platform Advantages . 4 2 Internal Architecture . 5 2.1 Introduction . 5 2.2 AMD-K6®-2 Processor Microarchitecture Overview . 5 Enhanced RISC86® Microarchitecture . 6 2.3 Cache, Instruction Prefetch, and Predecode Bits . 9 Cache . 9 Prefetching. 10 Predecode Bits . 10 2.4 Instruction Fetch and Decode . 11 Instruction Fetch . 11 Instruction Decode . 12 2.5 Centralized Scheduler . 14 2.6 Execution Units . 15 Register X and Y Pipelines . 16 2.7 Branch-Prediction Logic . 17 Branch History Table. 18 Branch Target Cache . 18 Return Address Stack . 18 Branch Execution Unit . 19 3 Software Environment . 21 3.1 Registers . 21 General-Purpose Registers . 22 Integer Data Types . 23 Segment Registers. 24 Segment Usage . 24 Instruction Pointer . 25 Floating-Point Registers . 25 Floating-Point Register Data Types. 28 MMX™/3DNow!™ Registers. 29 MMX™ Data Types . 29 3DNow!™ Data Types . 30 EFLAGS Register . 31 Control Registers. 32 Debug Registers. 34 Model-Specific Registers (MSR) . 37 Contents iii Preliminary Information AMD-K6®-2 Processor Data Sheet 21850J/0—February 2000 Memory Management Registers . 40 Task State Segment . 42 Paging . 43 Descriptors and Gates . 46 Exceptions and Interrupts . 49 3.2 AMD-K6®-2 Processor Model 8/[F:8] Registers . 50 Extended Feature Enable Register (EFER)–Model 8/[F:8] . 50 Write Handling Control Register (WHCR)–Model 8/[F:8] . 51 UC/WC Cacheability Control Register (UWCCR)52 Processor State Observability Register (PSOR). 53 Page Flush/Invalidate Register (PFIR) . 53 3.3 Instructions Supported by the AMD-K6®-2 Processor . 54 4 Signal Descriptions . 83 4.1 Signal Terminology . 83 4.2 A20M# (Address Bit 20 Mask) . 85 4.3 A[31:3] (Address Bus) . 86 4.4 ADS# (Address Strobe) . 87 4.5 ADSC# (Address Strobe Copy) . 87 4.6 AHOLD (Address Hold) . 88 4.7 AP (Address Parity) . 89 4.8 APCHK# (Address Parity Check) . 90 4.9 BE[7:0]# (Byte Enables) . 91 4.10 BF[2:0] (Bus Frequency) . 92 4.11 BOFF# (Backoff) . 93 4.12 BRDY# (Burst Ready) . 94 4.13 BRDYC# (Burst Ready Copy) . 95 4.14 BREQ (Bus Request) . 96 4.15 CACHE# (Cacheable Access) . 96 4.16 CLK (Clock) . 97 4.17 D/C# (Data/Code) . 97 4.18 D[63:0] (Data Bus) . 98 4.19 DP[7:0] (Data Parity) . 99 4.20 EADS# (External Address Strobe) . 100 4.21 EWBE# (External Write Buffer Empty) . 101 4.22 FERR# (Floating-Point Error) . 102 4.23 FLUSH# (Cache Flush) . 103 4.24 HIT# (Inquire Cycle Hit) . 104 4.25 HITM# (Inquire Cycle Hit To Modified Line) . 104 4.26 HLDA (Hold Acknowledge) . 105 4.27 HOLD (Bus Hold Request) . 105 4.28 IGNNE# (Ignore Numeric Exception) . 106 4.29 INIT (Initialization) . 107 4.30 INTR (Maskable Interrupt) . 108 4.31 INV (Invalidation Request) . 108 4.32 KEN# (Cache Enable) . 109 iv Contents Preliminary Information 21850J/0—February 2000 AMD-K6®-2 Processor Data Sheet 4.33 LOCK# (Bus Lock) . 110 4.34 M/IO# (Memory or I/O) . 111 4.35 NA# (Next Address) . 112 4.36 NMI (Non-Maskable Interrupt) . 112 4.37 PCD (Page Cache Disable) . 113 4.38 PCHK# (Parity Check) . 114 4.39 PWT (Page Writethrough) . 115 4.40 RESET (Reset) . 116 4.41 RSVD (Reserved) . 116 4.42 SCYC (Split Cycle) . 117 4.43 SMI# (System Management Interrupt) . 117 4.44 SMIACT# (System Management Interrupt Active) . 118 4.45 STPCLK# (Stop Clock) . 119 4.46 TCK (Test Clock) . 119 4.47 TDI (Test Data Input) . 120 4.48 TDO (Test Data Output) . ..