DIGITAL CMOS CIRCUIT DESIGN THE KLUWER INTERNATIONAL SERIES IN ENGINEERING AND COMPUTER SCIENCE VLSI, COMPUTER ARCHITECTURE AND DIGITAL SIGNAL PROCESSING Consulting Editor Jonathan Allen Other books in the series: Logic Minimization Algorithms for VLSI Synthesis. R.K. Brayton, G.D. Hachtel, C.T. McMullen, and A.L. Sangiovanni-Vincentelli. ISBN 0-89838-164-9. Computer-Aided Design and VLSI Device Development. K.M. Cham, S.-Y. Oh, D. Chin, and J.L. Moll. ISBN 0-89838-204-1. Adaptive Filters: Structures, Algorithms, and Applications. M.L. Honig and D.G. Messerschmitt. ISBN 0-89838-163-0. Introduction to VLSI Silicon Devices: Physics, Technology and Characterization. B. EI-Kareh and R.J. Bombard. ISBN 0-89838-210-6. Latchup in CMOS Technology: The Problem and Its Cure. R.R. Troutman. ISBN 0-89838-215-7. DIGITAL CMOS CIRCUIT DESIGN by Marco Annaratone Carnegie-Mellon University Pittsburgh, Pennsylvania .,~ KLUWER ACADEMIC PUBLISHERS Boston / Dordrecht / Lancaster Distributors for Nortb America: Kluwer Academic Publishers 101 Philip Drive ASsinippi Park Norwell, Massachusetts 02061, USA Distributors for tbe UK and Ireland: Kluwer Academic Publishers MTP Press Limited Falcon House, Queen Square Lancaster LAI lRN, UNITED KINGDOM Distributors for all otber countries: Kluwer Academic Publishers Group Distribution Centre Post Office Box 322 3300 AH Dordrecht, THE NETHERLANDS Library of Congress Cataloging-in-Publication Data Annaratone, Marco. Digital CMOS circuit design. (The Kluwer international series in engineering and computer science. VLSI, computer architecture, and digital signal processing) Includes index. 1. Metal oxide semiconductors, Complementary. 2. Digital electronics. 3. Integrated circuits­ Very large scale integration. I. Title. II. Series. TK7871.99.M44A56 1986 621.395 86-10646 ISBN-13: 978-1-4612-9409-2 e-ISBN-13: 978-1-4613-2285-6 001: 10.1007/978-1-4613-2285-6 Copyright © 1986 by Kluwer Academic Publishers All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, mechanical, photocopying, recording, or other­ wise, without the prior written permission of the publisher, Kluwer Academic Publishers, 101 Philip Drive, Assinippi Park, Norwell, Massachusetts 02061. Printed in the United States of America To Hanni (and Vanessa, ofcourse) Contents Foreword xi Preface xiii 1. Introduction 1 1.1. From nMOS to CMOS 3 1.2. CMOS Basic Gates 8 2. MOS Transistor Characteristics 15 2.1. The MOS Transistor 15 2.2. Parasitic Parameters 28 2.3. Small Geometry MOS Transistor 36 2.4. CMOS Transmission Gate 41 2.5. CMOS Inverter 44 2.6. A More Accurate Model for the CMOS Inverter 49 2.7. CMOS Power Dissipation 55 3. Fabrication Processes 61 3.1. The p-well Fabrication Process 62 3.2. The n-well Fabrication Process 66 3.3. LOCMOS Technology 68 3.4. Latchup 71 3.5. The Twin-tub Fabrication Process 79 3.6. The SOS Fabrication Process 80 3.7. Bulk vs. SOl 82 3.8. Design Rules 83 4. Logic Design 89 4.1. Static Logic 93 4.1.1. Complementary Logic 93 4.1.2. nMOS-like Logic 94 4.1.3. Transmission Gate Intensive Logic 98 4.1.4. Cascode Logic 100 4.2. Dynamic Logic 103 4.2.1. Ripple-through Logic 105 4.2.2. P-E Logic 111 viii Digital CMOS Circuit Design 4.2.3. Clocked CMOS Logic 113 4.2.4. Domino Logic 114 4.2.5. NORA Logic 117 4.3. Charge Sharing 121 4.4. Bootstrap Logic 124 4.5. Logic Design at the System Level 128 5. Circuit Design 133 5.1. Resistance, Capacitance, and Inductance 134 5.1.1. Interconnect Resistance 136 5.1.2. Interconnect Capacitance 137 5.1.3. Interconnect Inductance 143 5.1.4. Interconnect Discontinuities 143 5.1.5. Coupling Parameters and Interconnect Delay 144 5.1.6. Diffusion Resistance 146 5.1.7. Contact Resistance 147 5.2. Modeling Long Interconnects 149 5.3. The Concept of Equivalent Gate Load 152 5.4. Delay Minimization 155 5.4.1. Inverter Delay and Sizing 156 5.4.2. Inverter Chain Sizing 159 5.4.3. Inverter Chain Sizing with Stray Capacitance 162 5.5. Transistor Sizing in Static Logic 163 5.6. Transistor Sizing in Dynamic Logic 165 6. Design of Basic Circuits 173 6.1. Storage Elements 174 6.2. Full-adder 178 6.3. Programmable Logic Array 181 6.4. Random-access Memory 186 6.4.1. Memory Cell 188 6.4.2. Decoder 191 6.4.3. Sense Amplifier 193 6.5. Parallel Adder 204 6.6. Parallel Multiplier 209 6.6.1. The Design of a Multiplier Based on the Modified Booth Algorithm 211 6.6.2. Basic Building-blocks Inside the Array 213 6.6.3. The Problem of Sign Extension 216 6.6.3.1. The "Sign Propagate" Method 217 6.6.3.2. The "Sign Generate" Method 222 6.6.4. The Implementation of a 24-bit CMOS Booth Multiplier 226 Contents ix 7. Driver and I/O Buffer Design 233 7.1. CMOS Inverter Delay Estimation 234 7.1.1. Fall-time Delay Estimation 243 7.1.1.1. Region 1: n-channel Device in Saturation 244 7.1.1.2. Region 2: n-channel Device in Linear Region 248 7.1.2. Rise-time Delay Estimation 252 7.1.3. Refining the Model 252 7.2. Input Buffer 257 7.3. Output Buffer 261 7.4. Tri-state Output Buffer and I/O Buffer 272 7.5. Output Buffer and Bus Driver Design Optimization 274 7.5.1. Unconstrained Delay Minimization 275 7.5.2. Constrained Delay Minimization 282 7.6. Input Protection 287 7.7. Output Protection 294 7.8. Driving Large On-chip Loads 295 Appendix A. Layout 301 A.I. General Considerations on Layout 302 A.2. Layout Methodologies for Latchup Avoidance 310 A.3. Layout with Structured Methodologies 313 A.4. Power and Ground Routing 315 Appendix B. Interconnect Capacitance Computation 319 B.I. Case 1: Coupled Microstrip Structure 320 B.2. Case 2: Coupled Stripline Structure 321 Appendix C. Figures from Section 5.4.2 323 Appendix D. Delay Minimization Based on Eq. (7·3) 327 Appendix E. Equations Related to Fig. 7·10 337 Appendix F. Symbols and Physical Constants 339 Index 341 Foreword In light of decreasing feature size and greater sophistication of modern processing technology, CMOS has become increasingly attractive, pro­ viding low-power (at moderate frequencies), good scalability, and rail-to­ rail operation. For many designers, particularly those approaching VLSI from a system viewpoint, previous experience has been mainly with ratioed NMOS design, and so there is a need to build on this experience and make a natural transition into CMOS design. Indeed, there is much that can be bor­ rowed from NMOS experience, mainly centered around the techniques for creating N channel pulldown structures. Based on these contributions, CMOS has now grown to the point where there are several circuit styles which have evolved, and these are amply described in this book. Starting at the level of the individual MOSFET, basic building blocks are described, as well as the variety of CMOS fabrication processes in contemporary usage. Circuit style issues are then expanded to provide the user with several useful design methodologies, and much care is given to electrical performance con­ siderations, including characteristics of interconnect, gate delay, and I/O buffering. This understanding is then applied to macro-sized components, including array multipliers, where the reader acquires a unified view of ar­ chitectural performance through parallelism, and circuit performance through scrupulous attention to device sizing and control of parasitic circuit elements. In addition, layout techniques to avoid latchup, a consideration not previously encountered by NMOS designers, are given careful treatment. Designers who are approaching CMOS from previous NMOS experience, or those who are contemplating their first designs, will find a rich treatment of major design issues centered around CMOS, in a style that is thoughtful, detailed, and broad from the system perspective. The emerging high­ performance designs will partake of the benefits of increasingly exciting process and circuit innovation, forming the basis for lasting contributions to contemporary digital design. Jonathan Allen Consulting Editor Preface Complementary metal-oxide semiconductor (CMOS) technology has become the most effective fabrication process for the production of very large-scale integrated (VLSI) digital circuits. Moreover, there is wide-spread consensus that no other technology will effectively compete with CMOS for many years to come. It is therefore essential for the VLSI circuit designer to fully master the wide range of possibilities that CMOS can offer. The purpose of this book is not simply to present and discuss the most important techniques used in the design ofCMOS digital circuits. Rather, digital CMOS design is dealt with in the realm of constantly decreasing feature sizes, which poses new challenges to the designer in search ofultimate speed. A quick look at the Table of Contents exemplifies this: interconnection and off-chip communication delays are dealt with extensively in Chapters 5 and 7. As is well-known, the intrinsic gate delay no longer dictates circuit speed. Interconnection and off-chip communication delays represent far more important limitations. This is another reason why other technologies featuring shorter gate delay than CMOS - such as Gallium Arsenide, in particular - will not necessarily prevail in the short term. Smaller feature sizes will also require lower power supply voltage. Although it is still possible to use the standard 5V power supply for micrometer technologies, sub-rilicron processes will necessitate lower voltages. with dramatic effects on design methodologies. Lower voltages and smaller parasitic capacitances make dynamic logic design less reliable, noise problems may call for differential interconnections.