ELECTRICAL CHARACTERIZATION AND MODELING OF LATERAL DMOS TRANSISTOR – INVESTIGATION OF CAPACITANCE AND HOT CARRIER IMPACT PRESENTEE AU DEPARTEMENT D’ELECTRICITE ECOLE POLYTECHNIQUE FEDERAL DE LAUSANNE POUR L’OBTENTION DU GRADE DE DOCTEUR EN SCIENCES ET TECHNIQUES PAR Nasser HEFYENE LAUSANNE, EPFL 2005 CONTENTS CHAPTER 1: INTRODUCTION AND MOTIVATION 1. 1. High-Voltage and Power CMOS Evolution . 7 1. 2. High-Voltage and Power MOSFET Modeling Overview . 9 1. 2. 1. Models based on various levels of SPICE . 10 1. 2. 2. BSIM3V3 approach . 10 1. 2. 3. Empirical models . 10 1. 2. 4. Lumped-charge models . 11 1. 2. 5. Parameters for DMOS modelling . 11 1. 2. 6. Criteria for model evaluation . 11 1. 3. Conclusion and Motivation of this Work . 12 References . 13 CHAPTER 2: DMOS TRANSISTOR AND THE INTRINSIC DRAIN VOLTAGE CONCEPT 2. 1. High-Voltage DMOS Architectures . 16 2. 1. 1. LDMOS transistor architecture . 16 2. 1. 2. XDMOS transistor architecture . 16 2. 2. Numerically Simulated High-Voltage DMOS Architectures . 18 2. 3. Intrinsic-Drain Voltage (VK) Concept . 19 2. 3. 1. VK potential in DMOS architectures . 19 2. 3. 2. Drift-resistance vs. DMOS architectures . 22 2. 3. 3. Drain current in DMOS architectures . 24 2. 3. 4. Saturation mechanisms in DMOS architectures . 25 2. 4. Conclusion . 28 References . 29 CHAPTER 3: DRIFT RESISTANCE AND DC MODELING OF DMOS TRANSISTOR 3. 1. Intrinsic-MOS Region Modeling . 32 3. 2. DMOS Drift-Region Modeling . 33 3. 2. 1. Experimental base modeling approach . 33 3. 2. 2. Mathematically base modeling approach . 39 3. 2. 2. 1. MESDRIFT architecture . 39 3. 2. 2. 2. MESDRIFT characteristics . 41 3. 2. 2. 3. Bias-dependent drift-resistance modeling . 43 3. 3. DMOS Transistor Macro-Modeling . 51 3. 3. 1. DMOS modeling using experimental Rdrift mathematical expression . 51 3. 3. 2. DMOS modeling using mathematical Rdrift modeling approach . 53 3. 3. 2. 1. Extracted vs. modelled I-V characteristics at room-temperature . 53 3. 3. 2. 2. Extracted vs. modelled I-V characteristics at over temperature . 59 3. 3. 2. 3. Model scalability . 60 3. 4. DMOS Transistor Compact-Modeling . 63 3. 4. 1. DMOS compact-modeling using EKV simplified expression . 64 3. 4. 2. Extracted vs. modeling I-V characteristics at room-temperature . 68 3. 4. 3. Compact-modeling strategy . 73 3. 5. Conclusion . 75 References . 76 2 CHAPTER 4: DRIFT RESISTANCE AND AC MODELING OF DMOS TRANSISTOR 4. 1. Intrinsic-Drain Voltage (VK) Concept for AC DMOS Modeling . 79 4. 2. Small Signal Analysis . 81 4. 3. Large Signal Analysis . 85 4. 3. 1. Drift-region modeling - charge-based approach . 85 4. 3. 1. 1. Key constants and technological parameters . 85 4. 3. 1. 2. Fitting parameters . 86 4. 3. 1. 3. Drift-charges . 87 4. 3. 1. 4. Total drift-charge . 92 4. 3. 2. AC DMOS Modeling with BSIM3v3 . 93 4. 3. 3. AC DMOS Modeling with EKV (Long-channel Approximation) . 96 4. 5. Conclusion . 98 References . 99 CHAPTER 5: HOT CARRIER IMPACT ON THE CAPACITANCE OF DMOS TRANSISTORS AND RELIABILITY ISSUES 5. 1. Introduction . 101 5. 2. Device Architecture . 102 5. 3. Experimental Setup . 102 5. 4. Stress Conditions . 102 5. 4. 1. Stress-A . 104 5. 4. 2. Stress-B . 104 5. 5. DC Analysis of Hot Carrier Degradation . 104 5. 6. AC Analysis of Hot Carrier Degradation . 104 5. 7. Parameter Extraction . 105 5. 7. 1. DC parameters . 105 5. 7. 2. AC parameters . 106 5. 8. Parameter Extraction . 110 5. 8. 1. Gate Capacitance at VD = 0V . 110 5. 8. 2. Gate Capacitance at VD > 0V . 111 5. 9. Hot-Carrier Degradation at Room Temperature . 113 5. 9. 1. DC hot-carrier degradation analysis at room temperature . 113 5. 9. 2. Capacitance hot-carrier degradation analysis at room temperature . 118 5. 9. 3. Discussion at room temperature . 123 5. 9. 3. 1. Discussion of stress effect at maximum body current (stress-A) . 123 5. 9. 3. 2. Discussion of stress effect at maximum gate bias (stress-B) . 125 5. 9. 4. Conclusion: HC degradation at room temperature . 126 5. 10. Hot-Carrier Degradation as Function of Temperature . 127 5. 10. 1. Applied stress biases over temperature . 128 5. 10. 2. DC hot-carrier degradation analysis over temperature . 131 5. 10. 3. Capacitance hot-carrier degradation analysis over temperature . 136 5. 10. 4. Discussion of hot carrier degradation function of temperature . 141 5. 10. 4. 1. Discussion of stress effect at maximum body current (stress-A) . 141 5. 10. 4. 2. Discussion of stress effect at maximum gate bias (stress-B) . 141 5. 11. Conclusion . ..