Proceedings of the World Congress on Engineering and Computer Science 2016 Vol II WCECS 2016, October 19-21, 2016, San Francisco, USA Techniques of JFET Gate Capacitance Modeling Stanislav Bana´s,ˇ Josef Dobesˇ and Vaclav´ Pankoˇ Abstract—This paper presents various techniques and prin- : V ciples of modeling JFET gate capacitance. Various layout concepts as well as their gate capacitance measurements and `:1J Q%`HV modeling techniques are presented. Experience with potential modeling or measurement challenges is shared. The paper also U U U U U deals with an often-omitted tight interaction between C-V and R DC models, necessary for the well-fitting compact model. Good agreement has been achieved between measured silicon data %G `: V and SPICE simulations for all discussed layout variants. Plots of various layouts and various tests from real production models are also presented. Fig. 1. Cross-section of single-gate JFET (pinch resistor). Index Terms—JFET, SPICE model, gate capacitance, pinch- off voltage, p-n junction barrier capacitance. Voltage dependent capacitances CGD and CGS are usually I. INTRODUCTION represented by the compact diode SPICE models with the HE Junction Field Effect Transistor (JFET) is a com- voltage dependent p-n junction barrier capacitance described T ponent used in many applications, as for example low- by the equation [3], [4] noise amplifier, high input impedance amplifier, constant C current source, etc. [1]. It can be constructed as 3-terminal C = j0 AREA (1) Mj (3T) or 4-terminal (4T) component. The more complicated 1 − V 4T JFET contains two independently controlling gates, which Vj allow two input signals to be applied simultaneously, so it where Cj0 is the zero-bias junction capacitance per unit area, can be used in signal mixing applications [2]. Vj is junction built-in potential, Mj is grading coefficient, and Development of JFETs especially for high-voltage appli- AREA is the area of pn junction (representing the half of cations requires considering various aspects, as for example JFET gate area). optimization of breakdown voltage with series resistance, These compact diode SPICE models can be either part of ESD robustness, etc. Therefore, various JFET concepts can customized lumped macro-model or integrated in the JFET be found. Apart from that, the JFET can be found as a model as for example in R3 model [5]. parasitic structure in other components as for example in It is apparent, that low doped substrate and high doped high-voltage PMOS, which can be observed in measured P+ gate are connected in our three-terminal JFET, so the characteristics and should be considered in macro-model. question is, how to measure and evaluate model parameters This paper is focused on the modeling of JFET gate of CGD and CGS for the equation 1. The equation assumes a capacitance, which is seemingly only a simple p-n junction, physical p-n junction with depletion area spreading with the but in reality the measured C-V characteristics can at first applied p-n junction voltage, not two parallel p-n junctions look quite surprising. Various JFET concepts and measured affecting each other. gate capacitances including explained physical interpretation One of possible solutions is to measure the gate and of observed phenomena are presented. Modeling techniques substrate p-n junctions separately and implement two parallel (lumped model, behavioral model, etc.) are compared and diodes in the model instead of one. However, such solution plots with silicon data vs simulated results are demonstrated. does not correctly represent the real situation, where the JFET channel can be pinched off by a few volts. The separate II. SINGLE-GATE (THREE-TERMINAL) JFET measurements in artificial structures do not cover this case. The example of single-gate JFET cross-section is shown in It is more correct to measure the real situation of gate and Fig. 1, the related layout is in Fig. 2 and the typical macro- substrate connected in a real JFET device. In such a case, model is in Fig. 3. Such component is often called the pinch resistor and it is often used as a constant current source. Manuscript received June 30, 2016; revised July 12, 2016. This work was supported by ON Semiconductor company and by the Grant Agency of the `:1J : V Q%`HV Czech Technical University in Prague, grant No. SGS16/164/OHK3/2T/13. S. Bana´sˇ and V. Pankoˇ are with the ON Semiconductor, SGC Czech Design Center, Department of Design Systems Technology, 1.maje´ 2594, 756 61 Roznovˇ pod Radhostˇ em,ˇ Czech Republic and Czech Technical University in Prague, Faculty of Electrical Engineering, Department of Radioelectronics, Technicka´ 2, 166 27, Prague 6 , Czech Republic, e-mail: [email protected]. %G `: V$%:`R`1J$ J. Dobesˇ is with Czech Technical University in Prague, Faculty of Electrical Engineering, Department of Radioelectronics, Technicka´ 2, 166 27, Prague 6 , Czech Republic., email: [email protected] Fig. 2. Layout of single-gate JFET (pinch resistor). ISBN: 978-988-14048-2-4 WCECS 2016 ISSN: 2078-0958 (Print); ISSN: 2078-0966 (Online) Proceedings of the World Congress on Engineering and Computer Science 2016 Vol II WCECS 2016, October 19-21, 2016, San Francisco, USA : V Drain Source Sub : V `:1J IQRVC Q%`HV P Substrate Fig. 3. Simplified C-V macro-model of single-gate JFET (pinch resistor). Fig. 5. Cross-section of high-voltage dual-gate 4T JFET. however, the extracted parameters Vj and Mj can get quite far from their expected physical values, which especially occurs In any case it is necessary to measure the gate capacitance at low temperatures. In compact models the parameter Vj has in the real three-terminal structures containing drain, source the integrated temperature dependency [3] and gate terminals, and not (as is often practised) in large two-terminal customized p-n junction structures. If the JFET is too small and gate capacitance value is under tester T ni(Tnom) VJ (T ) = VJ (Tnom) + 2Vtln (2) measurement limit (sometimes called measurement noise Tnom ni(T ) floor), more JFETs in parallel can be used instead. Correct measurement of gate-drain capacitance CGD is with floating where T is simulation temperature, Tnom is nominal ref- erence temperature at which the values of basic model source, correct measurement of gate-source capacitance CGS is with floating drain. parameters were extracted, Vt is the thermal voltage and ni is the intrinsic carrier concentration of used material, in our Let us for simplicity only talk about measurement of case silicon, with its own temperature dependency [3] gate-drain capacitance CGD in the following text. In such a case the measured gate-drain capacitance CGD is equal to the sum of two parallel capacitances: gate-drain capacitance T Xti (direct p-n junction) and gate-source capacitance in series ni(T ) = ni(Tnom) with the source-drain resistance, which is basically a JFET Tnom represented by its DC model. When the gate-drain voltage q E (T ) E (T) exp ( G nom − G ) (3) V voltage across the p-n junction reaches the JFET pinch- 2k T T GD nom off voltage, the JFET body becomes fully depleted, and the where Xti is intrinsic carrier concentration temperature ex- mentioned second parallel path containing gate-source capac- ponent used in SPICE as a tunable temperature parameter, itance CGS is disconnected. This appears as a steep drop of typically set to the value 1.5, and EG is the gap width with capacitance in measured C-V characteristic, as demonstrated its own temperature dependency described in [6]. in Fig. 4. Measurement of the gate capacitance with shorted drain and source does not show this effect. The same effect Therefore, if the extracted VJ value gets too far from its expected physical value, it can become too low at very low was observed also in gate capacitances of MESFET/pHEMT or microwave varactors [7]. temperatures, and making V /Vj too dominant, in extreme case even larger than 1, which could cause negative capac- itance. The extracted parameters should thus be carefully III. DUAL-GATE (FOUR-TERMINAL) JFET verified in the full temperature range. If the verification fails An example of dual-gate JFET cross-section is shown in and obtaining precise voltage dependent capacitance with Fig. 5, the related layout is in Fig. 6 and the typical macro- the integrated model equation 1 becomes impossible, the model is in Fig. 7. This component is designed for high- alternative solution of behavioral voltage dependent capacitor voltage applications, therefore it has a circular or oval shape model can be used. with the high voltage pad in the center, as illustrated in Fig. 6. This configuration ensures that the high voltage applied to 4.5E-11 4.0E-11 IV:%`VR 1I%C: VR 3.5E-11 3.0E-11 2.5E-11 (F) 2.0E-11 GD C `:1JT GQJR1J$]:R 1.5E-11 1.0E-11 5.0E-12 0.0E+0 : V -30 -25 -20 -15 -10 -5 0 Q%`HV VGD (V) %G `: VT VHQJR$: V Fig. 4. CGD-V characteristic of single-gate JFET with full depletion at VGD = −15 V. Fig. 6. Layout of high-voltage dual-gate 4T JFET. ISBN: 978-988-14048-2-4 WCECS 2016 ISSN: 2078-0958 (Print); ISSN: 2078-0966 (Online) Proceedings of the World Congress on Engineering and Computer Science 2016 Vol II WCECS 2016, October 19-21, 2016, San Francisco, USA : V 1.E-11 IV:%`VR 1.E-11 1I%C: VR 1.E-11 YR YR `:1J IQRVC Q%`HV 8.E-12 (F) YR 6.E-12 YR SUBD C 4.E-12 %G `: V 2.E-12 YR 0.E+00 Fig.