Preliminary Draft May 19th 1992 Video Subsystem Preliminary Draft May 19th 1992 2 Preliminary Draft May 19th 1992 Video Subsystem Section 1. Introduction ....................... 1-1 Video Subsystem .......................... 1-2 Section 2. VGA Function ...................... 2-1 VGA Function Introduction ..................... 2-5 Major Components ......................... 2-7 Hardware Considerations ..................... 2-11 Modes of Operation ......................... 2-12 Video Memory Organization .................... 2-24 Registers ............................... 2-41 VGA Programming Considerations ................ 2-97 Video Digital-to-Analog Converter ............... 2-104 VGA Video Extensions ...................... 2-107 Section 3. XGA Function ...................... 3-1 XGA Function Introduction ..................... 3-7 VGA compatibility .......................... 3-16 132-Column Text Mode ....................... 3-16 Extended Graphics Mode ...................... 3-20 XGA Display Controller Registers ................. 3-34 Coprocessor Description ...................... 3-90 Coprocessor Registers ...................... 3-132 XGA System Interface ....................... 3-169 Virtual Memory Description ................... 3-177 | XGA Adapter Identification, Location and XGA Mode Setting 3-192 | VGA Modes ............................. 3-223 | Programming the XGA subsystem ............... 3-230 Section 4. Display Connector ................... 4-1 Display Connector Introduction .................. 4-2 Index .................................. X-1 Copyright IBM Corp. 1989, 1991 i Preliminary Draft May 19th 1992 ii Video Subsystem− May 7th 1992 Preliminary Draft May 19th 1992 Figures 2-1. Diagram of the VGA Function .............. 2-6 2-2. Graphics Controller .................... 2-9 2-3. Attribute Controller .................... 2-10 ! 2-4. BIOS Video Modes .................... 2-12 2-5. Double Scanning and Border Support ......... 2-13 2-6. Direct-Drive Analog Displays .............. 2-14 2-7. Character/Attribute Format ............... 2-16 2-8. Attribute Byte Definitions ................ 2-16 2-9. BIOS Color Set ...................... 2-17 2-10. Video Memory Format .................. 2-18 2-11. PEL Format, Modes Hex 4 and 5 ............ 2-19 2-12. Color Selections, Modes Hex 4 and 5 ......... 2-19 2-13. PEL Format, Mode Hex 6 ................ 2-20 2-14. Bit Definitions C2,C0 ................... 2-21 2-15. Compatible Color Coding ................ 2-23 2-16. 256KB Video Memory Map ............... 2-24 2-17. Data Flow for Write Operations ............. 2-39 2-18. Color Compare Operations ............... 2-40 2-19. Video Subsystem Register Overview ......... 2-41 2-20. General Registers .................... 2-42 2-21. Miscellaneous Output Register, Hex 03CC/03C2 .. 2-42 2-22. Display Vertical Size ................... 2-43 2-23. Clock Select Definitions ................. 2-43 2-24. Input Status Register 0, Hex 03C2 ........... 2-44 2-25. Input Status Register 1, Hex 03DA/03BA ....... 2-45 2-26. Feature Control Register, Hex 03DA/03BA and 03CA 2-46 2-27. Video Subsystem Enable Register, Hex 03C3 .... 2-46 2-28. Sequencer Registers ................... 2-47 2-29. Sequencer Address Register ............. 2-47 2-30. Reset Register, Index Hex 00 .............. 2-48 2-31. Clocking Mode Register, Index Hex 01 ........ 2-49 2-32. Map Mask Register, Index Hex 02 ........... 2-51 2-33. Character Map Select Register, Index Hex 03 .... 2-52 2-34. Character Map Select A ................. 2-53 2-35. Character Map Select B ................. 2-53 2-36. Memory Mode Register, Index Hex 04 ........ 2-54 2-37. Map Selection, Chain 4 ................. 2-54 2-38. CRT Controller Registers ................ 2-55 2-39. CRT Controller Address Register, Hex 03B4/03D4 . 2-56 2-40. Horizontal Total Register, Index Hex 00 ........ 2-56 Copyright IBM Corp. 1989, 1991 iii Preliminary Draft May 19th 1992 2-41. Horizontal Display Enable-End Register, Index Hex 01 .............................. 2-57 2-42. Start Horizontal Blanking Register, Index Hex 02 .. 2-57 2-43. End Horizontal Blanking Register, Index Hex 03 ... 2-58 2-44. Display Enable Skew ................... 2-58 2-45. Start Horizontal Retrace Pulse Register, Index Hex 04 .............................. 2-59 2-46. End Horizontal Retrace Register, Index Hex 05 ... 2-60 2-47. Vertical Total Register, Index Hex 06 ......... 2-61 2-48. CRT Overflow Register, Index Hex 07 ......... 2-62 2-49. Preset Row Scan Register, Index Hex 08 ....... 2-63 2-50. Maximum Scan Line Register, Index Hex 09 ..... 2-64 2-51. Cursor Start Register, Index Hex 0A .......... 2-65 2-52. Cursor End Register, Index Hex 0B .......... 2-66 2-53. Start Address High Register, Index Hex 0C ..... 2-67 2-54. Start Address Low Register, Index Hex 0D ...... 2-67 2-55. Cursor Location High Register, Index Hex 0E .... 2-68 2-56. Cursor Location Low Register, Index Hex 0F .... 2-68 2-57. Vertical Retrace Start Register, Index Hex 10 .... 2-69 2-58. Vertical Retrace End Register, Index Hex 11 ..... 2-69 2-59. Vertical Display-Enable End Register, Index Hex 12 2-71 2-60. Offset Register, Index Hex 13 .............. 2-71 2-61. Underline Location Register, Index Hex 14 ...... 2-72 2-62. Start Vertical Blanking Register, Index Hex 15 ... 2-73 2-63. End Vertical Blanking Register, Index Hex 16 .... 2-73 2-64. CRT Mode Control Register, Index Hex 17 ...... 2-74 2-65. CRT Memory Address Mapping ............ 2-75 2-66. Line Compare Register, Index Hex 18 ......... 2-77 2-67. Graphics Controller Register Overview ........ 2-78 2-68. Graphics Controller Address Register, Hex 03CE .. 2-78 2-69. Set/Reset Register, Index Hex 00 ........... 2-79 2-70. Enable Set/Reset Register, Index Hex 01 ....... 2-80 2-71. Color Compare Register, Index Hex 02 ........ 2-81 2-72. Data Rotate Register, Index Hex 03 .......... 2-82 2-73. Operation Select Bit Definitions ............ 2-82 2-74. Read Map Select Register, Index Hex 04 ....... 2-83 2-75. Graphics Mode Register, Index Hex 05 ........ 2-84 2-76. Write Mode Definitions .................. 2-85 2-77. Miscellaneous Register, Index Hex 06 ........ 2-86 2-78. Video Memory Assignments .............. 2-86 2-79. Color Don't Care Register, Index Hex 07 ....... 2-87 2-80. Bit Mask Register, Index Hex 08 ............ 2-88 2-81. Attribute Controller Register Addresses ....... 2-89 2-82. Address Register, Hex 03C0 .............. 2-89 2-83. Internal Palette Registers, Index Hex 00 - 0F ..... 2-90 iv Video Subsystem− May 7th 1992 Preliminary Draft May 19th 1992 2-84. Attribute Mode Control Register, Index Hex 10 ... 2-92 2-85. Overscan Color Register, Index Hex 11 ........ 2-94 2-86. Color Plane Enable Register, Index Hex 12 ..... 2-94 2-87. Horizontal PEL Panning Register, Index Hex 13 ... 2-95 2-88. Image Shifting ....................... 2-95 2-89. Color Select Register, Index Hex 14 .......... 2-96 2-90. Character Table Structure ............... 2-101 2-91. Character Pattern Example .............. 2-102 2-92. Split Screen Definition ................. 2-102 2-93. Screen Mapping within the Display Buffer Address Space ........................... 2-103 2-94. Video DAC Register .................. 2-104 2-95. Auxiliary Video Connector Interface ......... 2-108 2-96. Video Extension ..................... 2-109 2-97. Video Extension Signal Timing (DAC Signals) ... 2-111 | 3-1. XGA-NI Functional Enhancements ........... 3-9 3-2. XGA Video Subsystem .................. 3-10 | 3-3. MFI Alternate Attribute Select BIOS Call ....... 3-17 | 3-4. MFI Attribute Byte .................... 3-18 | 3-5. MFI Blink Rates ...................... 3-18 3-6. Intel Order of the XGA Memory Map ......... 3-21 3-7. Motorola Order of the XGA Memory Map ...... 3-22 3-8. CRT Controller Register Definitions .......... 3-24 3-9. Display PEL Map Offset and Width Definitions .... 3-25 3-10. Sprite Appearance Defined by 2-bit PEL ....... 3-26 3-11. Sprite Positioning ..................... 3-28 3-12. Direct Color Mode Data Word ............. 3-31 | 3-13. XGA Direct Color Palette Load ............. 3-32 3-14. Display Controller Register Addresses ........ 3-34 | 3-15. Operating Mode Register, Address Hex 21x0 .... 3-36 3-16. Display Mode Bit Assignments ............. 3-37 3-17. Aperture Control Register, Address Hex 21x1 .... 3-38 ! 3-18. Aperture Size and Location Bit Assignments .... 3-38 3-19. Interrupt Enable Register, Address Hex 21x4 .... 3-39 3-20. Interrupt Status Register, Address Hex 21x5 ..... 3-41 3-21. Aperture Index Register, Address Hex 21x8 ..... 3-43 3-22. Aperture Index Bit Assignments ............ 3-43 3-23. Memory Access Mode Register, Address Hex 21x9 3-44 3-24. PEL Size Bit Assignments ................ 3-44 3-25. Index Register, Address Hex 21xA ........... 3-45 3-26. XGA Index Register Assignments (Part I) ....... 3-45 3-27. XGA Index Register Assignments (Part II) ...... 3-45 | 3-28. Auto-Configuration Register, Index Hex 04 ...... 3-48 | 3-29. System Interface Bus Size ............... 3-48 | 3-30. System Bus Type ..................... 3-48 Video Subsystem− May 7th 1992 v Preliminary Draft May 19th 1992 3-31. Horizontal Total Registers, Indexes Hex 10 and 11 . 3-50 3-32. Horizontal Total Registers Value Assignments ... 3-50 3-33. Horizontal Display End Registers, Indexes Hex 12 and 13 ............................ 3-51 3-34. Horizontal Display End Registers Value Assignments 3-51 3-35. Horizontal Blanking Start Registers, Indexes Hex 14 and 15 ............................ 3-52 3-36. Horizontal Blanking Start Registers Value Assignments .......................