Payam Heydari Address : 830 Childs Way, SUITE #254 Los Angeles, CA 90089 Tel : (213) 740-4437 Home: (323) 730-0883 Fax : (213) 740-7290 E-mail : [email protected] EDUCATION: 1996-present: Ph.D. - Electrical Engineering - University of Southern California - GPA : 3.95/4.0 Ph.D. Advisor : Professor Massoud Pedram Thesis Title: Noise Analysis and Optimization in High-Frequency Mixed-Signal VLSI Circuits 1993-1995: M.Sc. - Electrical Engineering - Sharif University of Technology - GPA : 3.85/4.0 M.Sc. Advisor : Professor Kambiz Nayebi Thesis Title: A High Quality Mixed Excitation LPC Vocoder for Low Bit-rate Speech Coding 1987-1992: B.Sc. - Electrical Engineering - Sharif University of Technology - GPA : 3.5/4.0* * The average undergraduate GPA at the Sharif University of Tech. is 2.9/4.0. INTERNSHIP: Summer 1997: Bell laboratories, Lucent Technologies, Murray Hill, NJ. Summer 1998: IBM T. J. Watson Research Center, Yorktown Heights, NY. HONORS & AWARDS: • Best Iranian Graduate Student in the area of Electrical Engineering in Southern California, 2001 • Technical Excellence Award from Association of Professors and Scolars of Iranian Heritage, 2001 • Best Paper Award, IEEE International Conference on Computer Design, Austin, Texas, 2000. • Recipient of Travel grant, ASP-DAC conference, Yokohama, Japan, Feb. 2001. • Recipient of Young Student Award, Design Automation Conference, Los Angeles, 2000. • Honorable Mention Award, Department of EE-Systems, University of Southern California, 2000. • Ranked 2nd amongst M.Sc. graduate students, Sharif University of Technology, 1995. • Ranked 10th in the nationwide examination for postgraduate studies, Iran, 1993. • Ranked 5th among more than 200,000 applicants in the nationwide entrance examination, Iran, 1987. • Ranked 1st among more than 25,000 students in regional scientific olympiad, Iran, 1987. RESEARCH/WORK EXPERIENCE: 2000-present Graduate Research assistant, Model-Reduction Project, University of Southern California - Worked on a new variational spectrally-weighted balanced truncation technique for order reduc- tion of variable-geometry interconnects - Worked on a new spectrally weighted balanced truncation technique for order reduction of on- chip interconnects - Worked on a very efficient and accurate model for analyzing the crosstalk noise in high-frequency VLSI circuits 1999-2000 Graduate Research Assistant, Phase-Locked Loop Project, University of Southern California - Designed a 2.5V, 0.25µ CMOS PLL with lock-range of 50MHz-400MHz - Proposed an accurate analytical expression and novel analysis for the jitter-induced power/ground bounce noise in CMOS PLLs - Worked on the analysis and optimization of power/ground bounce in VLSI circuits - Designed a 10-bit 2Msamples/sec two-step flash A/D converter - Simulated and analyzed a 14-bit oversampled Σ-∆ D/A Converter 1998 Summer Internship, IBM Thomas J. Watson Research Center, Yorktown Heights, NY - Worked on gradient-based optimization of custom integrated circuits - Worked on a new comprehensive formulation for adjoint sensitivity analysis of digital switched- mode circuits 1997 Summer Internship, Bell laboratories, Lucent Technologies, Murray Hill, NJ - Designed a user interface program for CLOVER (Circuit LayOut Verifier) tool. - Worked on a new crosstalk noise metric for predicting the peak value and noise pulse width of the crosstalk noise 1996-1997 Graduate Research Assistant, University of Southern California - Worked on the time and frequency domain analysis of lossy on-chip interconnects in ulta high-fre- quency VLSI circuits - Worked on the transistor-level power reduction of DSP chips 1996 Design Engineer, Saravel Inc. - Designed and Implemented a special purpose 4.8Kbit/sec modem 1995-1996 Design Engineer, Keresm Communications - Simulated the RPE-LTP speech vocoder of a GSM mobile handset using C program - Simulated audio and video compression system used in B-ISDN network 1995 Graduate Reseach Assistant, M.Sc. Project, Sharif University of Technology - Designed and implemented a new low bit-rate mixed excitation LPC vocoder system 1992-1994 Member of Technical Staff, Electronics Research Center, Sharif University of Technology - Designed and implemented a Power Line Carrier (PLC) system used for based-band transmission of data and speech over the power lines - Designed and implemented a narrow-band high frequency BPF : (fc = 30MHz, BW=100kHz). - Designed and implemented a high frequency, low voltage ripple switch-mode power supply - Designed and implemented a real-time speech scrambling system using Hartley transform and time reversed segmentation technique PUBLICATIONS: • Payam Heydari, Massoud Pedram, “Ground Bounce in Digital VLSI Circuits,” Submitted to IEEE Trans. on VLSI Systems • Payam Heydari, Massoud Pedram, “Model Reduction of Variable-Geometry Interconnects Using Varia- tional Spectrally-Weighted Balanced Truncation,” IEEE International Conference on Computer-Aided Design (ICCAD), San Jose, CA, Nov. 2001 • Payam Heydari, Massoud Pedram, “Analysis and Reduction of Capacitive Coupling Noise in High- speed VLSI Circuits,” IEEE International Conference on Computer Design (ICCD), Austin, Texas, September 2001 • Payam Heydari, Massoud Pedram, “Jitter-Induced Power/Ground Noise in CMOS PLLs: A Design Per- spective,” to appear in IEEE International Conference on Computer Design (ICCD), Austin, Texas, September 2001 • Payam Heydari, Massoud Pedram, “Balanced Truncation with Spectral Shaping for RLC Intercon- nects,” IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, JAPAN, Feb. 2001 • Payam Heydari, Massoud Pedram, “Analysis and Optimization of Ground Bounce in Digital CMOS Circuits,” IEEE International Conference on Computer Design (ICCD), September 2000 (Best Paper Award for ICCD 2000) • Payam Heydari and Massoud Pedram, "Analysis of Jitter due to Power-Supply Noise in Phase-Locked Loops," SRC TECHCON, Paper 10.6, Phoenix, AZ, September 2000 • Payam Heydari, Massoud Pedram, “Analysis of Jitter due to Power-Supply Noise in Phase-Locked Loops,” IEEE Custom Integrated Circuits Conference (CICC), Orlando, FL, May 2000 (Honorable Mention Award from USC) • Payam Heydari, Massoud Pedram, “Analysis of Off-chip and On-chip Simultaneous Switching Noise in VLSI Circuits,” SRC TECHCON, paper 14.8, Las Vegas, NV, September 1998 • Payam Heydari, Massoud Pedram, “Calculation of Ramp Response of Lossy Transmission Lines Using Two-port Network Functions,” ACM International Symposium on Physical Design, April 1998 • Payam Heydari, Kambiz Nayebi, ‘A New Mixed Excitation LPC Vocoder, Design and Implementation,’ M.Sc. thesis, Sharif University of Technology, 1995 MEMBERSHIP IN PROFESSIONAL ORGANIZATIONS: IEEE, ACM/SIGDA, IGSA GRADUATE- LEVEL COURSES: Mixed Signal VLSI Circuit Design Linear System Theory Computer-Aided Design of Digital Systems I , II Advanced Topics in Electronic Circuits Design Advanced Computer Architecture RF Microelectronics Digital Signal Processing I , II Digital Speech and Image Processing Communication circuits Advanced Communications theory Advanced logic design and switching theory Operating Systems Fourier Optics COMPUTER SKILLS: Program Languages : C/C++, FORTRAN, 80x86 Assembly languages, TI TMS320C2X Assembly lan- guage. Tools : MAGIC, SIS, IRSIM, HSPICE, Matlab, OrCAD, PROTEL, Timberwolf, Bear. TEACHING EXPERIENCE: 1996-1997 : Teaching assistant, (EE 483) Introduction to Digital Signal Processing, USC. Fall 1995 : Teaching assistant, Telecommunications I, Sharif University of Technology. Spring 1995 : Teaching assistant, Digital Signal Processing, Sharif University of Technology. Spring 1995 : Teaching assistant, Signals and Systems, Sharif University of Technology. Fall 1993 : Teaching assistant, Communication Circuits, Sharif University of Technology. Spring 1990 : Teaching assistant, Electronics III, Sharif University of Technology..