US 20190268023A1 ( 19) United States (12 ) Patent Application Publication ( 10) Pub . No. : US 2019 /0268023 A1 Freudenberger et al. (43 ) Pub. Date : Aug . 29, 2019 (54 ) METHOD AND DEVICE FOR ERROR GIIC 29 /52 ( 2006 .01 ) CORRECTION CODING BASED ON HO3M 13 / 15 ( 2006 .01 ) HIGH - RATE GENERALIZED (52 ) U . S . CI. CONCATENATED CODES CPC . .. .. HO3M 13 / 253 ( 2013 .01 ) ; HO3M 13 /293 ( 2013 . 01 ) ; GIIC 29 / 52 ( 2013. 01 ) ; HO3M (71 ) Applicant: HYPERSTONE GMBH , Konstanz 13 /152 (2013 .01 ) ; H03M 13 / 2906 (2013 .01 ) ; (DE ) HO3M 13/ 1515 (2013 . 01 ) ; HO3M 13 / 1505 (72 ) Inventors : Juergen Freudenberger, Radolfzell ( 2013 . 01 ) (DE ) ; Jens Spinner , Konstanz (DE ) ; Christoph Baumhof , Radolfzell (DE ) ( 57 ) ABSTRACT (21 ) Appl. No. : 16/ 395 ,046 ( 22 ) Filed : Apr. 25 , 2019 Field error correction coding is particularly suitable for applications in non - volatile flash memories. We describe a Related U . S . Application Data method for error correction encoding of data to be stored in (63 ) Continuation of application No. 15 /593 , 973, filed on a memory device, a corresponding method for decoding a May 12 , 2017 , now Pat. No . 10 , 320 , 421. codeword matrix resulting from the encoding method , a coding device , and a computer program for performing the ( 30 ) Foreign Application Priority Data methods on the coding device , using a new construction for high - rate generalized concatenated (GC ) codes . The codes , May 13 , 2016 (DE ) . .. .. .. 102016005985 . 0 which are well suited for error correction in flash memories Apr. 6 , 2017 (DE ) . 102017107431 . 7 for high reliability data storage , are constructed from inner nested binary Bose -Chaudhuri - Hocquenghem (BCH ) codes Publication Classification and outer codes, preferably Reed - Solomon (RS ) codes . For ( 51 ) Int. Ci. the inner codes extended BCH codes are used , where only HO3M 13 / 25 ( 2006 .01 ) single parity - check codes are applied in the first level of the H03M 13 / 29 ( 2006 .01 ) GC code . This enables high -rate codes . 650555 # * # ihiticitations 555 titititi dico t ididid soo itivinididididididos 66000 FA + + 000000 MEREHANI HOST 75+ pipa - D2 mm 00000000000000000000 - C2 MAX90X0000090XXX0099xX600X9099X000099/4coooo SodexX666666000 0 0000 XXXXXXXXX * * Woxx0XCUSEGG ! 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Patent Application Publication Aug . 29 , 2019 Sheet 3 of 5 US 2019 / 0268023 A1 ra = n = 7 = (S1 ) Matrix D ? = 1 WA San Outer enconding aze | ago | 240 250 26, (S2 ) Matrix A 211 , 22, | 23, 24, 1 | a51 26, 1 53 24 , 1 ( S3 ) 240 Inner enconding Matrix C Tooxx + XonxeoXXXSCOXWCa Sóc BCH parity portion of b4 (1 ) Fig . RA3 Patent Application Publication Aug . 29 , 2019 Sheet 4 of 5 US 2019 / 0268023 A1 data matrix ??? ??????? + PC decoder BCH reimage RS decoder - ? BO 4 4 ??? ??? TSO - T ) - 4 ?? ?? - ?? - BCH reencoding - teration * ?? - * (S0 - 5 ) * ???? ?- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - -- - - - - - - - -- - - -- WHY MNHHWWMWAX MARRRRRRRRRRYWHY KARYAWARMHXHNAMMYUNUNHAMNARRARROARRAY TRRRRRRRRRRYYYYKKYMXN KWNRXWXXERAMKAAR ???? BCH decoder BCH reimage RS decoder ? ??? ??? t ?? r ?????. - ?.????? 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X W 2684-120 *WWWWWWWWWWWW MYTHE mhurmannunáwww.annunciowowakuuheranan KILAKXXXXXNLLZLILILXAXXXKZKL Press yWWW XLXXKXXKKI ALLAH XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXEERSMEX 0 . 85 YYYYYYYYYYY WWW WMPINARARAM* XXXXXX XKXXHXWXURSANWALXMHR EKKXXE pouco maisKXXXXXX em WHAT * * * GC code , hard Input WWWWWWWWWWWWWWWWWWWWWWWWWWUWMV E wwwwwwww VDARRARAAMAMARA A mov MWWWWWWWWW MAMA COM Fig . 5 US 2019 /0268023 A1 Aug . 29 , 2019 METHOD AND DEVICE FOR ERROR SUMMARY OF THE INVENTION CORRECTION CODING BASED ON [0006 ] It is accordingly an object of the invention to HIGH - RATE GENERALIZED provide a method and device for error correction coding CONCATENATED CODES which overcome the above -mentioned and other disadvan tages of the heretofore - known devices and methods of this CROSS - REFERENCE TO RELATED general type and which provide , in particular, for improved APPLICATION code rates . Specifically , it is desirable that such methods and devices are suitable for improved ECC encoding / decoding [ 0001 ] This application is a continuation of U . S . patent of data in connection with the storage / reading of the data application Ser. No . 15 /593 , 973 of the same title and having in / from a memory, such as a non -volatile memory . the same inventor, and filed May 12 , 2017 ; which in turn 10007 ]. With the foregoing and other objects in view there claims priority under 35 USC $ 119 , of German patent is provided , in accordance with the invention , a method of application DE 10 2016 005 985 . 0 , filed May 13 , 2016 , and error correction encoding of data to be stored in a memory of German patent application DE 10 2017 107 431. 7 , filed device , the method comprising : Apr. 6 , 2017 . Each of the aforementioned applications is [0008 ] providing a coding device ; incorporated by reference for all purposes . 10009 ] using the coding device to subject the data to error correction encoding based on generalized concatenated cod ing (GCC ) to obtain encoded data ; wherein : BACKGROUND OF THE INVENTION 100101 the GCC is constructed from L inner nested binary extended Bose - Chaudhuri -Hocquenghem (BCH ) codes and Field of the invention L outer codes , where L22 and L is a positive integer; [ 0011 ] an extended BCH code in a lowest nesting level of [0002 ] The present invention relates to the field of error the inner nested BCH codes is a mere single parity - check correction coding , in particular for applications in non ( SPC ) code ; and volatile flash memories. Specifically , the invention is [0012 ] an extended BCH code in at least one higher directed to a method of error correction encoding of data to nesting level of the inner nested BCH codes has an error be stored in a memory device , a corresponding method for correction capability and is a sub - code of the BCH code of decoding a codeword matrix resulting from the encoding the lowest nesting level . method , a coding device adapted to perform one or more of [0013 ] A first aspect of the invention is directed to a these methods , and a corresponding computer program for method of error correction encoding of data to be stored in performing said methods on the coding device . a memory device, the method being performed by a coding [ 0003 ] Error correction coding (ECC ) based on General device and comprising applying error correction encoding ized Concatenated Codes (GC codes ) has a high potential for based on generalized concatenated coding, GCC , to the data various applications in data communication and data storage to obtain encoded data . Therein , ( i ) the GCC is constructed systems, e , g ., for digital magnetic storage systems as from L inner nested binary extended Bose - Chaudhuri - Hoc described n reference [ 1 ] ( see list of references [ . ] at the quenghem , BCH , codes and L outer codes , preferably Reed end of written specification ) , for non - volatile flash memories Solomon codes (RS - codes ) , wherein L22 is a positive inte ( cf . [ 2 ] ) , and for two -dimensional bar codes ( cf. [ 3 ] ) . In ger , ( ii ) the extended BCH code in the lowest nesting - level particular, GC codes may be used for error correction in of the inner nested BCH codes is a mere single parity - check , flash memories as proposed in [ 2 ] and [ 4 ] . SPC , code , and ( iii ) the extended BCH code in at least one higher nesting - level of the inner nested BCH codes has an [ 0004 ] In particular , such GC codes may be constructed error correction capability ( in contrast to the SPC code , from inner nested binary Bose -Chaudhuri - Hocquenghem which can only detect certain errors ) and is a sub -code of the (BCH ) codes and outer Reed -Solomon (RS ) codes , as gen BCH code of the lowest nesting level . erally described for example in [ 5 ] , [ 6 ] and [ 7 ] , and are well [0014 . The term “ extended BCH code , ” as used herein , suited for fast hardware decoding architectures (cf . [ 4 ] ) . In refers to a code the codewords of which generally comprise coding theory, the BCH codes form a class of linear cyclic both a BCH codeword and an additional single parity check error - correcting codes that are constructed using finite fields ( SPC ) symbol ( i.