Boolean Logic Optimization in Majority-Inverter Graphs Luca Amaru,´ Pierre-Emmanuel Gaillardon, Giovanni De Micheli Integrated Systems Laboratory (LSI), EPFL, Switzerland. Abstract— We present a Boolean logic optimization framework based to the data-structure/methodology fitness, our MIG Boolean methods on Majority-Inverter Graph (MIG). An MIG is a directed acyclic graph have an efficient runtime, i.e., can handle 100k equivalent gates in consisting of three-input majority nodes and regular/complemented edges. less than a minute, on a standard laptop. Our Boolean methods Current MIG optimization is supported by a consistent algebraic frame- work. However, when algebraic methods cannot improve a result quality, are simple, yet powerful. Experiments combined with state-of-art stronger Boolean methods are needed to attain further optimization. For MIG algebraic techniques show tremendous results. For example, this purpose, we propose MIG Boolean methods exploiting the error when targeting depth reduction, our MIG optimizer automatically masking property of majority operators. Our MIG Boolean methods transforms a ripple carry adder into a carry look-ahead one. Con- insert logic errors that strongly simplify an MIG while being successively masked by the voting nature of majority nodes. Thanks to the data- sidering the set of IWLS’05 (arithmetic intensive) benchmarks, our structure/methodology fitness, our MIG Boolean methods run in principle MIG optimizer reduces by 17.98%(26.69%) the logic network depth as fast as algebraic counterparts. Experiments show that our Boolean while also enhancing size and power activity metrics, with respect to methodology combined with state-of-art MIG algebraic techniques en- ABC tool [13]. Without MIG Boolean methods, using MIG algebraic able superior optimization quality. For example, when targeting depth reduction, our MIG optimizer transforms a ripple carry adder into optimization alone, only (about) half of the aforementioned gains a carry look-ahead one. Considering the set of IWLS’05 (arithmetic appeared in our experiments. Employed as front-end to a delay- intensive) benchmarks, our MIG optimizer reduces by 17.98% (26.69%) critical 22-nm ASIC flow (logic synthesis + physical design) our MIG the logic network depth while also enhancing size and power activity optimizer reduces the average delay/area/power by (15.07%, 4.93%, metrics, with respect to ABC academic optimizer. Without MIG Boolean 1.93%), over 27 academic and industrial benchmarks, as compared methods, i.e., using MIG algebraic optimization alone, the previous gains are halved. Employed as front-end to a delay-critical 22-nm ASIC flow to a leading commercial ASIC flow. (logic synthesis + physical design) our MIG optimizer reduces the average The remainder of this paper is organized as follows. Section II delay/area/power by (15.07%, 4.93%, 1.93%), over 27 academic and provides a background on logic optimization and on MIGs. Section industrial benchmarks, as compared to a leading commercial ASIC flow. III discusses on the logic flexibility of MIGs, exploiting the intrinsic Categories and Subject Descriptors voting resilience of majority nodes. Section IV describes our Boolean B.6.3 [Design Aids]: Automatic Synthesis, Optimization optimization methodology based on MIGs. Section V shows the General Terms experimental results for our MIG Boolean optimization employed Algorithms, Design, Performance, Theory. either stand-alone or as front-end to a commercial ASIC design flow. Keywords Section VI concludes the paper. Majority Logic, Boolean Optimization, Logic Synthesis. II. BACKGROUND AND MOTIVATION I. INTRODUCTION This section gives a background on logic optimization and MIGs. Nowadays, EDA tools are challenged by design goals at the frontier of what is achievable in advanced technologies. In this A. Logic Optimization scenario, recent logic synthesis works considered (slower) Boolean Logic optimization methods are usually divided into two groups: methods [1]–[5] rather than (faster) algebraic methods [6]–[9] to Algebraic methods, which are fast, and Boolean methods, which are obtain superior circuit realizations, in terms of speed, power and slower but achieve better results [10]. Traditional algebraic methods area. Indeed, it is desirable to spend more time in logic synthesis treat a logic functions as a polynomial [6], [7]. Algebraic operations computation to get a better final design. However, with traditional are selectively iterated over the entire logic circuits, until an improve- tools, there is a limit after which spending more effort in logic ment exists. Basic algebraic operations are extraction, decomposition, synthesis, for example running complex Boolean methods, does not factoring, balancing and substitution [10]. Their efficient runtime improve a circuit quality or even requires too long runtime [10]. is enabled by weak-division and kernel theory. Instead, Boolean To push this limit as far as possible, innovative data structures and methods handle the true nature of a logic function using Boolean manipulation laws are decisive. identities as well as (global) don’t cares (circuit flexibilities) to Majority-Inverter Graph (MIG) is a promising data structure for get a better solution [10], [12]. Boolean division and substitution logic optimization and synthesis recently introduced by [11]. An MIG techniques trade off runtime for better minimization quality. Most is a directed acyclic graph consisting of three-input majority nodes Boolean methods run on expressive data-structures, with ideally and regular/complemented edges. MIG manipulation is supported by no ambiguity on the representation. Canonical logic representation a consistent algebraic framework. Algebraic optimization of MIGs forms, such as truth tables and binary decision diagrams, support showed strong synthesis results. However, the heuristic and local efficiently Boolean methods. For example, Boolean decomposition (short-sighted) nature of MIG algebraic methods [11] might preclude based on binary decision diagrams can recognize re-structuring global (far-sighted) optimization opportunities. opportunities not visible by algebraic counterparts [3]–[5]. Modern In this paper, we extend the capabilities of MIG logic optimization optimization methodologies, and associated tools, use algebraic and by developing powerful Boolean methods based on majority voting. Boolean methods in conjunction [9], [13], i.e., after a slow but Our MIG Boolean methods enforce simplification opportunities by powerful Boolean method is used fast algebraic methods are repeated inserting logic errors successively masked by MIG nodes. Thanks until an improvement exists. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed B. Majority-Inverter Graph for profit or commercial advantage and that copies bear this notice and the full citation Majority-Inverter Graph on the first page. Copyrights for components of this work owned by others than ACM A (MIG) is a data structure for Boolean must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, function representation and optimization. An MIG is a logic net- to post on servers or to redistribute to lists, requires prior specific permission and/or a work consisting of 3-input majority nodes and regular/complemented fee. Request permissions from [email protected]. DAC ’15, June 07 - 11, 2015, San Francisco, CA, USA Copyright 2015 ACM 978- edges [11]. Each majority node can be reduced to a conjunction 1-4503-3520-1/15/06$15.00 http://dx.doi.org/10.1145/2744769.2744806 (AND) or a disjunction (OR) operator by fixing the third input to 0 or to 1, respectively. It follows that any AND/OR-INV graphs Notation A logic circuit f affected by an error A is written as f A. (AOIG) can be emulated by a structurally identical MIG. In Fig. 1, For example, considering the function , an error an example AOIG is depicted with its structurally, and functionally, f = (a + b)· c A defined as ”stuck variable to ” ( : ) leads to A . identical MIG. However, even better MIG representations appear by b 0 A b = 0 f = ac In general, an error flips k entries in the truth table of the affected f% f% function. In the previous example, k =1. If k =0, the error is safe AOIG%!%MIG% MIG%!%MIGopt% f% or permissible, as it does not change the original functionality [17]. AND% MAJ% To insert safe (permissible) errors in an MIG we consider a root MAJ% node w and we triplicate it. In each version of w we introduce OR% 1% MAJ% x3% logic errors heavily simplifying the MIG. Then, we connect back OR% 1% MAJ% MAJ% MAJ% the three faulty versions of w to a top majority node exploiting the error masking property. Unfortunately, a majority node cannot x2% x3% x3% x2% x1% x0% x3% x2% x1% 1% x0% x1% x0% 1% 1% mask all types of errors. This limits our choice of permissible Fig. 1: Example of MIG representation. errors. Orthogonal errors, defined1 hereafter, fit with our purposes. exploiting MIG nodes functionality (majority) rather than reducing Informally, two logic errors are orthogonal if for any input pattern it to AND/OR. Again in Fig. 1, a more compact MIG for the same they cannot happen simultaneously. example is depicted, having one fewer level of depth and the same Definition Two logic errors A and B on a logic circuit f are said number of nodes. To natively optimize and reach advantageous MIGs, orthogonal if (f A ⊕ f)· (f B ⊕ f)=0. like the one in Fig. 1, a MIG Boolean algebra is introduced in [11] To give an example about orthogonal errors consider the function and axiomatized (Ω) by five primitive transformation rules. f = (a + b)· c. Here, the two errors A: a + b = 1 and B: c = 0 Ω Commutativity – .C are actually orthogonal. Indeed, by simple logic simplification, we ′ ′ M(x, y, z)= M(y, x, z)= M(z,y,x) get (c ⊕ f)· (0 ⊕ f) = (((a + b)c) c + ((a + b)c)c )· ((a + b)c) = Majority – Ω.M ′ ((a + b)c) c· ((a + b)c)=0.