Power Management Using FPGA Architectural Features Abu Eghan, Principal Engineer Xilinx Inc

Power Management Using FPGA Architectural Features Abu Eghan, Principal Engineer Xilinx Inc

Power Management Using FPGA Architectural Features Abu Eghan, Principal Engineer Xilinx Inc. Agenda • Introduction – Impact of Technology Node Adoption – Programmability & FPGA Expanding Application Space – Review of FPGA Power characteristics • Areas for power consideration – Architecture Features, Silicon design & Fabrication – now and future – Power & Package choices – Software & Implementation of Features – The end-user choices & Enablers • Thermal Management – Enabling tools • Summary Slide 2 2008 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc Technology Node Adoption in FPGA • New Tech. node Adoption & level of integration: – Opportunities – at 90nm, 65nm and beyond. FPGAs at leading edge of node adoption. • More Programmable logic Arrays • Higher clock speeds capability and higher performance • Increased adoption of Embedded Blocks: Processors, SERDES, BRAMs, DCM, Xtreme DSP, Ethernet MAC etc – Impact – general and may not be unique to FPGA • Increased need to manage leakage current and static power • Heat flux (watts/cm2) trend is generally up and can be non-uniform. • Potentially higher dynamic power as transistor counts soar. • Power Challenges -- Shared with Industry – Reliability limitation & lower operating temperatures – Performance & Cost Trade-offs – Lower thermal budgets – Battery Life expectancy challenges Slide 3 2008 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc FPGA-101: FPGA Terms • FPGA – Field Programmable Gate Arrays • Configurable Logic Blocks – used to implement a wide range of arbitrary digital functions. • Programmable I/O Blocks • Routing resources • Switch matrix and interconnects/pass gates • Configuration -- Modern configuration memory & Platform Configuration states FPGA • Key FPGA attribute – regardless of what heterogeneous functions and elements are incorporated - is the ability to implement arbitrary digital logic circuit. Slide 4 2008 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc FPGA Attributes • The upside – some unique attributes – Need more transistors to implement solutions – due to programmability overhead. – Die size is relatively large – power density is moderate. – More “standby” or “passive” resources – reduced power density • Menu of packages offered - with broad heat handling capability, • Software & programmability Opportunities to deal with power at the implementation level – Flexible and Optional Architectural features • The challenge to Packaging – Flexibility means end-user power needs are largely unknown – Tailored thermal solution – no such luck Slide 5 2008 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc Market & Their Needs Where FPGAs are used Today • Markets: Revenue by End Market – Wired/wireless infrastructure High-end FPGA equipment – base stations Data Consumer Industrial – Modular racks in storage/servers Processing & Auto & Other – Consumer & Automotive – Telematics 15% & entertainment 8% 32% – Industrial & Mil/Aero – battle tanks, planes, radar etc 45% • Common requirement – Bigger, faster, cheaper! – Reduce the need for heatsinks or at Communications least the cost of thermal solution – Lower power supply overhead & complexity Slide 6 2008 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc Power Density in Platform FPGA Source: Xilinx XPE data reported by Priya Sundararajan etc al ICCAD ‘06 • Density Uniformity no longer “a given” • But the magnitude remains manageable – trade up density for efficiency Slide 7 2008 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc The Relative Magnitude of FPGA Power • For high performance Approx Components Offerings – FPGAs are in the Power 1 – 10watts/cm2 2006/8 High End • For small devices this is well 10 – 30 Watts below 1 watt/cm2, and FPGA typically less than 0.5. 2002 K7-AMD • Relative to Processors & Mobile/2006 AMD Graphics Chips, FPGA power Turion density is “lukewarm”, but can INTEL Mobile – 10 – 35 Watts eg 2002 P4 or Range surprise some users 2004 Pm • Conventional Pkg Air cooling; Solutions already exist - Rsa Transmetta 88 series • How can we make this a non- issue? Today’s FPGA Power relative to early 2000 Mobile Processor Power Slide 8 2008 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc The 2 Power Components 1. Static: • Power from Transistor leakage or bias Current • The larger the device (>> transistors) the higher this component • Programmable transistors in FPGAs add to this power • It is not activity based, but increases with temperature • Gets worse with newer (leaky transistor) technologies. 2. Dynamic: • Activity based – similar to other ICs • Depends on switching frequency, Capacitance and Voltage levels • Improves with newer smaller nodes – for same design • Remains relatively flat with temperature Slide 9 2008 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc Power Consumption Breakdown • FPGA Power Consumption is design dependent • XC3S1000 at 100MHz, with 12.5% toggle rate, typical resource utilization. • Breakdown shows areas in silicon & implementation that can yield good results Slide 10 2008 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc Focus • Question: – How can we leverage the features of the FPGA architecture, the flexibility of FPGA (programmability & placement) to address Power Management challenges? • Answer: – Some of the work and features are discussed - Balance of discussion – Focus areas grouped into 4 broad areas encompassing Architecture & Silicon, menu of packages, Design & Implementation software, and thermal management tools and models. Slide 11 2008 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc The Focus Areas (Reduce Generation & Improve Removal) • Architecture improvements in Silicon - design & fabrication Physical Design ( • The Package menu: FCBGA with Architecture Features, consistent TIM for high powered Circuits & Process) products, down to small form factor Package Choices (like QFN) for hand-held Power Management • Software implementation of End- user design –Programmability, ISE Software flexibility & smart design Options – Power Optimization like I/O choices etc Low Power Design Enabling the end-user to make their System-Level Design – • Choices and Enabling contributions Tools & Models – Thermal Management – Enabling tools – Thermal Models etc Slide 12 2008 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc Considerations - 1 Physical Design ( Architecture Features, Circuits & Process) The Silicon: Package Choices Power Management Design & Implementation contribution to Heat ISE Software Power Optimization generation System-Level Design – Addressing Low Power Design Choices and Enabling Tools & Models Slide 13 2008 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc Static Power Increases Dramatically with Temperature ICCINTQ vs Junction Temperature 7 ICCINTQ 6 gate 100100 °°CC 5 sourceIGATE drain IS→D 8585 °°CC 4 Current Current 3 Normalized Leakage Normalized Leakage 2 2525 °°CC 1 0 -40 -20 0 20 40 60 80 100 120 140 Junction Temp °C Slide 14 2008 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc FPGA Power Components • XC3S1000 Slide 15 2008 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc Mixed-Oxide Technology • Leakage current increases as channel length and gate oxide thickness decrease • Same oxide thickness is not needed in Source all the transistors Metal Connection • A low-leakage “Midox” transistor type is used to reduce leakage in configuration memory cells Gate Oxide – varying thicknesses on die. • Transistors with longer channel length Channel 6 C) C) º and higher threshold are used through º 5 130nm Trend out the FPGA to reduce static power 4 50 % Lower 3 Power • Eg.130nm to 90nm can reduce static 2 Relative Static Power Static Relative Relative Static Power Static Relative 1 90nm FPGA Trend (Worst Case process & 85 process Case (Worst power by 50% at 100K gate level. & 85 process Case (Worst 0 0 25K 50K 75K 100K 125K 150K 175K 200K Logic Cells Slide 16 2008 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc Dynamic Power Component • Dynamic Power – P = kCV2f where FPGA Core Dynamic Power Trend k = Nodes switching C = Capacitance per node V = Voltage switching f = switching frequency or toggle rate 130nm • Reduced Core dynamic power 100 – Internal operating voltage is the 90nm dominant factor (1.5 =>1.2=>1.0) 80 NodeNode CapacitanceCapacitance – Secondary scaling by frequency dropsdrops 60 and node capacitance 65nm – Dynamic power consumption is addressed with low capacitance 40 circuits and custom blocks VoltageVoltage dropsdrops – Each successive node helps to 20 Relative Core Power % reduce power – same gate count Relative Core Power % – I/O dynamic power – gain limited 0 100 80 60 40 20 0 – Similar capacitance, voltage and Relative Capacitance or Voltage frequency is required to support industry I/O standards Slide 17 2008 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc Hard IPs As Power Saving Feature • Architecture Features – Larger logic blocks; smaller RAMs – Embedded hard- blocks give >10X power efficiency over soft-IPs • Trades moderate power density for overall lower power Slide 18 2008 MEPTEC Symposium “The Heat is On” Abu Eghan, Xilinx Inc Why Hard-IPs help • Reduced Static Power – No extra transistors as in programmable logic – No programmable interconnect transistors • Reduced Dynamic Power – Lower switching Transistor count – Metal Interconnects vs. Metal and programmable interconnects Î low interconnect capacitance – Reduced trace lengths – No extra node capacitance because of lack of pass transistors – Minimized

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