Intel387TM SX MATH COPROCESSOR Y New Automatic Power Management Y Compatible with the Intel386TM SX Ð Low Power Consumption Microprocessor Ð Typically 100 mA in Dynamic Mode, Ð Extends CPU Instruction Set to and 4 mA in Idle Mode Include Trigonometric, Logarithmic, and Exponential Y Socket Compatible with Intel387 Family of Math CoProcessors Y High Performance 80-Bit Internal Ð Hardware and Software Compatible Architecture Ð Supported by Over 2100 Commercial Y Implements ANSI/IEEE Standard Software Packages 754-1985 for Binary Floating-Point Ð 10% to 15% Performance Increase Arithmetic on Whetstone and Livermore Benchmarks Y Available in a 68-Pin PLCC Package See Intel Packaging Specification, Order Ý231369 The Intel387TM SX Math CoProcessor is an extension to the Intel386TM SX microprocessor architecture. The combination of the Intel387TM SX with the Intel386TM SX microprocessor dramatically increases the process- ing speed of computer application software that utilizes high performance floating-point operations. An internal Power Management Unit enables the Intel387TM SX to perform these floating-point operations while maintain- ing very low power consumption for portable and desktop applications. The internal Power Management Unit effectively reduces power consumption by 95% when the device is idle. The Intel387TM SX Math CoProcessor is available in a 68-pin PLCC package, and is manufactured on Intel's advanced 1.0 micron CHMOS IV technology. 240225±22 Intel386 and Intel387 are trademarks of Intel Corporation. *Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. January 1994 Order Number: 240225-009 © COPYRIGHT INTEL CORPORATION, 1995 1 Intel387TM SX Math CoProcessor CONTENTS PAGE CONTENTS PAGE 1.0 PIN ASSIGNMENT ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5 4.0 HARDWARE SYSTEM INTERFACE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21 1.1 Pin Description Table ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6 4.1 Signal Description ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22 2.0 FUNCTIONAL DESCRIPTION ÀÀÀÀÀÀÀÀÀ 7 4.1.1 Intel386 CPU Clock 2 2.1 Feature List ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7 (CPUCLK2) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22 2.2 Math CoProcessor Architecture ÀÀÀÀÀÀ 7 4.1.2 Intel387 Math CoProcessor 2.3 Power Management ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8 Clock 2 (NUMCLK2) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22 2.3.1 Dynamic Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8 4.1.3 Clocking Mode (CKM) ÀÀÀÀÀÀÀÀÀ 23 2.3.2 Idle Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8 4.1.4 System Reset (RESETIN) ÀÀÀÀÀÀ 23 2.4 Compatibility ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8 4.1.5 Processor Request (PEREQ) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 23 2.5 Performance ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8 4.1.6 Busy Status (BUSYÝ) ÀÀÀÀÀÀÀÀÀ 23 3.0 PROGRAMMING INTERFACE ÀÀÀÀÀÀÀÀÀ 9 4.1.7 Error Status (ERRORÝ) ÀÀÀÀÀÀÀ 23 3.1 Instruction Set ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 9 4.1.8 Data Pins (D15±D0) ÀÀÀÀÀÀÀÀÀÀÀ 23 3.1.1 Data Transfer Instructions ÀÀÀÀÀÀ 9 4.1.9 Write/Read Bus Cycle Ý 3.1.2 Arithmetic Instructions ÀÀÀÀÀÀÀÀÀÀ 9 (W/R ) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 23 Ý 3.1.3 Comparison Instructions ÀÀÀÀÀÀÀ 10 4.1.10 Address Stobe (ADS ) ÀÀÀÀÀÀÀ 23 3.1.4 Transcendental 4.1.11 Bus Ready Input Ý Instructions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 10 (READY ) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 24 3.1.5 Load Constant Instructions ÀÀÀÀ 10 4.1.12 Ready Output (READYOÝ) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 24 3.1.6 Processor Instructions ÀÀÀÀÀÀÀÀÀ 11 4.1.13 Status Enable (STEN) ÀÀÀÀÀÀÀÀ 24 3.2 Register Set ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 11 4.1.14 Math CoProcessor Select 1 3.2.1 Status Word (SW) Register ÀÀÀÀ 12 (NPS1Ý) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 24 3.2.2 Control Word (CW) 4.1.15 Math CoProcessor Select 2 Register ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 15 (NPS2) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 24 3.2.3 Data Register ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 16 4.1.16 Command (CMD0Ý) ÀÀÀÀÀÀÀÀÀ 24 3.2.4 Tag Word (TW) Register ÀÀÀÀÀÀÀ 16 4.1.17 System Power (VCC) ÀÀÀÀÀÀÀÀÀ 24 3.2.5 Instruction and Data 4.1.18 System Ground (VSS) ÀÀÀÀÀÀÀÀ 24 Pointers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 16 4.2 System Configuration ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 25 3.3 Data Types ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 18 4.3 Math CoProcessor Architecture ÀÀÀÀÀ 26 3.4 Interrupt Description ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 18 4.3.1 Bus Control Logic ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 26 3.5 Exception Handling ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 18 4.3.2 Data Interface and Control 3.6 Initialization ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21 Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 26 3.7 Processing Modes ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21 4.3.3 Floating Point Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀ 26 3.8 Programming Support ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21 4.3.4 Power Management Unit ÀÀÀÀÀÀÀ 26 2 2 CONTENTS PAGE CONTENTS PAGE 4.4 Bus Cycles ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 26 7.0 ELECTRICAL 4.4.1 Intel387 SX Math CHARACTERISTICS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 33 CoProcessor Addressing ÀÀÀÀÀÀÀÀÀÀ 27 7.1 Absolute Maximum Ratings ÀÀÀÀÀÀÀÀÀ 33 4.4.2 CPU/Math CoProcessor Synchronization ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 27 7.2 D.C. Characteristics ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 34 4.4.3 Synchronous/Asynchronous 7.3 A.C. Characteristics ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 35 Modes ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 27 8.0 Intel387 SX MATH COPROCESSOR 4.4.4 Automatic Bus Cycle INSTRUCTION SET ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 41 Termination ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 27 APPENDIX AÐIntel387 SX MATH 5.0 BUS OPERATION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 27 COPROCESSOR COMPATIBILITY ÀÀÀÀ A-1 5.1 Non-pipelined Bus Cycles ÀÀÀÀÀÀÀÀÀÀ 28 A.1 8087/80287 Compatibility ÀÀÀÀÀÀÀÀÀ A-1 5.1.1 Write Cycle ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 28 A.1.1 General Differences ÀÀÀÀÀÀÀÀÀÀ A-1 5.1.2 Read Cycle ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 29 A.1.2 Exceptions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ A-2 5.2 Pipelined Bus Cycles ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 29 APPENDIX BÐCOMPATIBILITY 5.3 Mixed Bus Cycles ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 30 BETWEEN THE 80287 AND 8087 5.4 BUSYÝ and PEREQ Timing MATH COPROCESSOR ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ B-1 Relationship ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 32 6.0 PACKAGE SPECIFICATIONS ÀÀÀÀÀÀÀÀ 33 6.1 Mechanical Specifications ÀÀÀÀÀÀÀÀÀÀ 33 6.2 Thermal Specifications ÀÀÀÀÀÀÀÀÀÀÀÀÀ 33 3 3 CONTENTS PAGE CONTENTS PAGE Figure 7-2 CPUCLK2/NUMCLK2 FIGURES Waveform and Figure 1-1 Intel387 SX Math Measurement Points for CoProcessor Pinout ÀÀÀÀÀÀÀÀÀÀÀ 5 Input/Output ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 38 Figure 2-1 Intel387 SX Math Figure 7-3 Output Signals ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 38 CoProcessor Block Figure 7-4 Input and I/O Signals ÀÀÀÀÀÀÀÀ 39 Diagram ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7 Figure 7-5 RESET Signal ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 39 Figure 3-1 Intel 386 SX CPU and Intel387 Math CoProcessor Figure 7-6 Float from STEN ÀÀÀÀÀÀÀÀÀÀÀÀÀ 40 Register Set ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 11 Figure 7-7 Other Parameters ÀÀÀÀÀÀÀÀÀÀÀÀ 40 Figure 3-2 Status Word ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 12 TABLES Figure 3-3 Control Word ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 15 Table 1-1 Pin Cross ReferenceÐ Figure 3-4 Tag Word Register ÀÀÀÀÀÀÀÀÀÀÀ 16 Functional Grouping ÀÀÀÀÀÀÀÀÀÀÀ 5 Figure 3-5 Instruction and Data Pointer Table 3-1 Condition Code Image in Memory, 32-Bit Interpretation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 13 Protected Mode Format ÀÀÀÀÀÀ 17 Table 3-2 Condition Code Interpretation Figure 3-6 Instruction and Data Pointer after FPREM and FPREM1 Image in Memory, 16-Bit Instructions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14 Protected Mode Format ÀÀÀÀÀÀ 17 Table 3-3 Condition Code Resulting Figure 3-7 Instruction and Data Pointer from Comparison ÀÀÀÀÀÀÀÀÀÀÀÀÀ 14 Image in Memory, 32-Bit Real Mode Format ÀÀÀÀÀÀÀÀÀÀÀ 17 Table 3-4 Condition Code Defining Operand Class ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14 Figure 3-8 Instruction and Data Pointer Image in Memory, 16-Bit Table 3-5 Mapping Condition Codes to Real Mode Format ÀÀÀÀÀÀÀÀÀÀÀ 18 Intel386 CPU Flag Bits ÀÀÀÀÀÀÀÀ 14 Figure 4-1 Intel386 SX CPU and Table 3-6 Intel387 SX Math Intel387 SX Math CoProcessor Data Type CoProcessor System Representation in Memory ÀÀÀÀ 19 Configuration ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 25 Table 3-7 CPU Interrupt Vectors Figure 5-1 Bus State Diagram ÀÀÀÀÀÀÀÀÀÀÀ 28 Reserve for Math CoProcessor ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 20 Figure 5-2 Non-Pipelined Read and Write Cycles ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 29 Table 3-8 Intel387 SX Math CoProcessor Exceptions ÀÀÀÀÀÀ 20 Figure 5-3 Fastest Transition to and from Pipelined Cycles ÀÀÀÀÀÀÀÀ 30 Table 4-1 Pin Summary ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22 Figure 5-4 Pipelined Cycles with Wait Table 4-2 Output Pin Status during States ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 31 Reset ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 23 Figure 5-5 BUSYÝ and PEREQ Timing Table 4-3 Bus Cycle Definition ÀÀÀÀÀÀÀÀÀÀ 26 Relationship ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 32 Table 6-1 Thermal Resistances Figure 7-1a Typical Output Valid Delay (§C/Watt) iJC and iJA ÀÀÀÀÀÀÀÀ 33 vs Load Capacitance at Max Table 6-2 Maximum TA at Various Operating Temperature ÀÀÀÀÀÀ 37 Airflows ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 33 Figure 7-1b Typical Output Slew Time vs Table 7-1 D.C. Specifications ÀÀÀÀÀÀÀÀÀÀÀ 34 Load Capacitance at Max Operating Temperature ÀÀÀÀÀÀ 37 Table 7-2a Timing Requirements of the Bus Interface Unit ÀÀÀÀÀÀÀÀÀÀÀÀ 35 Figure 7-1c Maximum ICC vs Frequency ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 37 Table 7-2b Timing Requirements of the Execution Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 36 Table 7-2c Other AC Parameters ÀÀÀÀÀÀÀÀÀ 36 Table 8-1 Instruction Formats ÀÀÀÀÀÀÀÀÀÀÀ 41 4 4 Intel387TM SX MATH COPROCESSOR 1.0 PIN ASSIGNMENT include VCC and VSS planes for power distribution and all VCC and VSS pins must be connected to the The Intel387 SX Math CoProcessor pinout as appropriate plane. viewed from the top side of the component is shown in Figure 1-1. VCC and VSS (GND) connections must NOTE: be made to multiple pins. The circuit board should Pins identified as N.C. should remain completely unconnected. 240225±1 Figure 1-1. Intel387TM SX Math CoProcessor Pinout Table 1-1. Pin Cross ReferenceÐFunctional Grouping BUSYÝ 36 D00 19 VCC 4VSS 5 N.C. 1 PEREQ 56 D01 20 9 14 10 ERRORÝ 35 D02 23 13 21 17 D03 8 22 25 18 ADSÝ 47 D04 7 26 27 52 CMD0Ý 48 D05 6 31 32 65 NPS1Ý 44 D06 3 33 34 67 NPS2 45 STEN 40 D07 2 37 38 68 D08 24 39 42 W/RÝ 41 D09 28 43 55 READYÝ 49 D10 29 46 60 READYOÝ 57 D11 30 50 61 D12 16 58 63 CKM 59 D13 15 62 66 CPUCLK2 54 D14 12 64 NUMCLK2 53 D15 11 RESETIN 51 5 5 Intel387TM SX MATH COPROCESSOR 1.1 Pin Description Table The following table lists a brief description of each pin on the Intel387 SX Math CoProcessor.