ISSN: 2277-3754 ISO 9001:2008 Certified International Journal of Engineering and Innovative Technology (IJEIT) Volume 2, Issue 6, October 2012 Performance of Turbo Encoder and Turbo Decoder for LTE Patel Sneha Bhanubhai, Mary Grace Shajan, Upena D. Dalal Latency 1. Control-plane: Less than 100 msec to Abstract— LTE (Long Term Evolution) is the upcoming establish U-plane standards towards 4G, which is designed to increase the capacity 2. User-plane: Less than 10 msec from UE and throughput performance when compared to UMTS and to Server WiMax. Turbo codes are the recent development in the area of Mobility 1. Optimized for low speeds (0-15 km/hr) forward error correction codes that achieve near-Shannon limit 2. High performance at speeds up to 120 performance.This codes have been successfully implemented in km/hr satellite and video conferencing systems and provision has been 3. Maintain link at speeds up to 350 km/hr made in 3rd generation mobile systems. The decoder systems are Coverage 1. Full performance up to 5 km compared for complexity as well as for equal numbers of 2. Slight degradation 5 km – 30 km iterations. The following figure shows the bit error rate 3. Operation up to 100 km should not be performance of the parallel concatenated coding scheme in an precluded by standard AWGN channel over a range of Eb/No values for two sets of code block lengths and number of decoding iterations. Results show II. TURBO CODES that less complex decoder strategies produce good results for voice quality bit error rates. Turbo codes were first introduced in 1993 by Berrou, Glavieux, and Thitimajshima, [2] where a scheme is Index Terms— Convolutional Interleaver, Turbo encoder described that achieves a bit-error probability of 10-5 using a Turbo decoder, MAP decoder, 3GPP LTE. rate 1/2 code over an additive white Gaussian noise (AWGN) channel and BPSK modulation at an Eb/N0 of 0.7 dB. The I. INTRODUCTION codes are constructed by using two or more component codes Long Term Evolution [1] has long been seen as the first on different interleaved versions of the same information advancement towards stronger, faster and more efficient 4G sequence. Turbo codes are a high performance forward error data networks. The technology under LTE can currently reach correction at a given code rate. These codes are especially downlink peak rates of 100Mbps and uplink speeds of used in deep space satellite communication and the 50Mbit/s. The LTE technology is also a scalable bandwidth application, which requires reliable transformation of technology for carriers operating anywhere from 20 MHz information over the communication links in the presence of town to 1.4 MHz. Long Term Evolution offers some excellent data corrupting noise. At present, these codes are competing advantages over current 3G systems including higher with Low Density Parity Check (LDPC) codes, which throughput, plug and play compatibility, FDD (Frequency produce similar performance. Turbo code implementation is Division Duplexing) and TDD (Time Division Duplexing), by a parallel concatenation of two recursive systematic low latency and lower operating expenditures. It also offers convolutional encoder codes depend on pseudo-random legacy modes to support devices operating on GPRS systems, permutation (the interleaver). The encoder performs a long bit while supporting seamless pass-through of technologies information frame. The interleaver to produce permuted operating on other older cellular towers. The authors of the frame interleaves this input bit. The first encoder RSC1 (Global system for mobile communications) and UMTS encodes the original input and the interleaved frame (Universal Mobile Telecommunications System). The (permuted frame) is encoded by RSC2. Then the two encoded technologies put forth by LTE will not only be implemented bits are merged together with the real input bits to produce the over time, they are designed to be scalable. This scalability output. means the company can slowly introduce LTE technologies over time, without disrupting current services. III. FUNDAMENTAL TURBO CODES Table I. Lte Performance Requirements [5]. The fundamental turbo code encoder is built using two Metric Requirements identical recursive systematic convolutional (RSC) codes Spectral Flexibility 1.4, 3, 5, 10, 15 and 20 MHz with parallel concatenation [3] as shown in Figure 1. An RSC Peak data rate 1. Downlink (2 Ch MIMO): 100 Mbps encoder is typically a rate 1/2 encoder and is termed a 2. Uplink (Single Ch Tx): 50 Mbps (20 constituent encoder. The input to the second constituent MHz ch) encoder is interleaved using an internal turbo code Supported antenna 1. Downlink: 4x2, 2x2, 1x2, 1x1 interleaver. Only one of the systematic outputs from the two configurations. 2. Uplink: 1x2, 1x1 component encoders is used. This is because the systematic Spectrum efficiency 1. Downlink: 3 to 4 times HSDPA Rel. 6 2. Uplink: 2 to 3 times HSUPA Rel. 6 125 ISSN: 2277-3754 ISO 9001:2008 Certified International Journal of Engineering and Innovative Technology (IJEIT) Volume 2, Issue 6, October 2012 output from the other component encoder is just a permuted which is the case for downlink and uplink data transmission, version of the chosen systematic output. paging and broadcast multicast (MBMS) transmissions. A rate 1/3 tail biting convolutional coding is used for downlink Xk control and uplink control as well as broadcast control Ck RSC encoder 1 channel (BCH). Zk DL-SCH Turbo code UL-SCH internal interleaver RSC encoder 2 Z’k Turbo Coding (1/3) PCH Fig 1: Turbo Code Encoder [3] MCH BCH Tail biting Convolutional DCI Coding (1/3) UCI Block Code w/ variable Rate Block Code 1/16 CFI Fig 3: Channel Coding Schemes in the LTE System [3]. VI. TURBO DECODER STRUCTURE Fig 2: Conventional Convolution Encoder and Equivalent RSC Encoder [3] The basic structure of a Turbo decoder is functionally illustrated in Fig.2. A turbo decoder consists of two maximum IV. MATH a posteriori (MAP) decoders separated by an interleaver that A conventional convolution encoder shown in [Fig. 2] is permutes the input sequence. The decoding is an iterative represented by the generator sequences process in which the so-called extrinsic information is g0(D) = 1+D2+D3 and exchanged between MAP decoders. Each Turbo iteration is g1(D) = 1+D+D3……………………………………..(1) divided in to two half iterations. During the first half iteration, It can equivalently be represented in a more compact form as MAP decoder 1 is enabled. It receives the soft channel G = [g0(D), g1(D)]………………………….(2) information (soft value Ls for the systematic bit and soft value The RSC encoder of this conventional convolutional encoder Lp1 for the parity bit) and the a priori information La1 from is represented as the other constituent MAP decoder through deinterleaving to G(D) =[1,g1(D)/g0(D)]……………………..(3) generate the extrinsic information Le1 at its output. Likewise, where the first output represented by g0(D) is fed back to the during the second half iteration, MAP decoder 2 is enabled, input. In the above representation, 1 denotes the systematic and it receives the soft channel information (soft value Ls for a output, g1(D) denotes the feed-forward output and g0(D) is permuted version of the systematic bit and soft value Lp 2 for the feedback to the input of the RSC encoder. the parity bit) and the a priori information La2 from MAP decoder1 through interleaving to generate the extrinsic V. CHANNEL CODING SCHEME IN LTE information Le2 at its output. This iterative process repeats The major channel coding schemes [3] used for different until the decoding has converged or the maximum number of transport channels in the LTE system are summarized in iterations has been reached. Figure 3. The turbo coding is used for large data packets, 126 ISSN: 2277-3754 ISO 9001:2008 Certified International Journal of Engineering and Innovative Technology (IJEIT) Volume 2, Issue 6, October 2012 In order to verify the Verilog HDL models for the interleaver and deinterleaver the authors have developed another top level Verilog HDL model, combining interleaver and deinterleaver [8]. The scrambled code words from the output of the interleaver is applied as input to the deinterleaver block along with clock as synchronization signal. It is observed in Fig 4 that the scrambled code word is converted into its original form at the output of the deinterleaver block. VIII. SOFTWARE MODEL Fig 4: Basic Structure of an Iterative Turbo Decoder [4]. VII. CONVOLUTIONAL INTERLEAVER A convolutional interleaver consists of N rows of shift registers, with different delay in each row. In general, each successive row has a delay which is J symbols duration higher than the previous row as shown in Fig. 5. The code word symbol from the encoder is fed into the array of shift registers, one code symbol to each row. With each new code word symbol the commutator switches to a new register and the new code symbol is shifted out to the channel. The i-th (1 ≤ i ≤ N-1) shift register has a length of (i-1)J stages where J = M/N and the last row has M-1 numbers of delay elements. Fig 7: Parallel Concatenated Convolutional coding: Turbo codes [7] Table II. RESULTS Block 512 BER-1024 BER-2048 length Eb/No BER 0 0.4825 0.4875 0.4906 3 0.4757 0.4829 0.4879 6 0.4655 0.4765 0.4829 9 0.4519 0.4668 0.4755 12 0.4327 0.4517 0.4657 [A]. Turbo Encoder Software Model Fig 5: Convolutional Interleaver [4] The convolutional deinterleaver performs the inverse operation of the interleaver and differs in structure of the arrangement of delay elements.