IETE Technical Review ISSN: 0256-4602 (Print) 0974-5971 (Online) Journal homepage: http://www.tandfonline.com/loi/titr20 Timing Closure Problem: Review of Challenges at Advanced Process Nodes and Solutions Sneh Saurabh, Hitarth Shah & Shivendra Singh To cite this article: Sneh Saurabh, Hitarth Shah & Shivendra Singh (2018): Timing Closure Problem: Review of Challenges at Advanced Process Nodes and Solutions, IETE Technical Review To link to this article: https://doi.org/10.1080/02564602.2018.1531733 Published online: 22 Oct 2018. Submit your article to this journal View Crossmark data Full Terms & Conditions of access and use can be found at http://www.tandfonline.com/action/journalInformation?journalCode=titr20 IETE TECHNICAL REVIEW https://doi.org/10.1080/02564602.2018.1531733 Timing Closure Problem: Review of Challenges at Advanced Process Nodes and Solutions Sneh Saurabh, Hitarth Shah and Shivendra Singh Department of ECE, IIIT, Delhi, India ABSTRACT KEYWORDS Attaining timing closure marks the culmination of an arduous VLSI design process. The targets set Advanced process nodes; for timing closure and the time taken to achieve it can critically impact the success of a product Design flow; Gate-delay; in a highly competitive semiconductor market. Therefore, methodologies employed in VLSI design Process variations; Timing process are strategized to attain quick timing closure along with reasonable design metrics. How- closure; Wire-delay ever, at advanced process nodes, attaining timing closure becomes quite challenging. As a result, at advanced process nodes, innovative solutions are required to be incorporated in VLSI design processes, as well as in Electronic Design Automation (EDA) tools and technologies. In this review paper, we discuss timing closure problem explaining the root cause of its difficulty. We also explain traditional techniques that address timing closure problem. Furthermore, we highlight new chal- lenges that appear at advanced process nodes and discuss solutions to these problems that are being employed or are proposed in literature. 1. INTRODUCTION a given design and have a critical impact on the com- Designing an integrated circuit is a complicated process petitiveness of the corresponding product in the semi- and involves making trade-offs among several conflicting conductor market [5]. Therefore, timing closure is an design parameters. To simplify the overall design pro- importantaspectofadesignflowandacarefulattention cess, the full flow is broken down into several distinct must be paid to it right from the beginning of a design stepsthatarecarriedoutoneafterother,asshownin process. Figure 1(a). The design starts with a specification and istakenthroughaseriesoftransformationandabstract At each stage of a design process, several aspects of a representation. Some of the critical steps in the design circuit such as functionality, timing, area, power, testa- flowarelogicsynthesis,floorplanning,placement,clock bility, yield, and reliability are examined and verified. tree synthesis and routing. At the end of the design flow, The operation of each design step can be modeled as an alayoutisobtained. interaction between a design database, an analysis engine andanimplementationengineasshowninFigure1(b). Before sending the final layout of a circuit to a foundry A design database contains appropriate information of forfabrication,asetofdesignparametersandrulesare a design such as design hierarchy, the interconnection checked.Thesefinalchecksareknownassignoffchecks of gates (netlist), timing constraints, floorplan, etc. An andensurethatthefabricatedchipwillbeabletomeet analysis engine computes or estimates design parameters the given specification. Among signoff checks, verify- related to timing, power, testability, etc. An implementa- ing whether a circuit is able to meet the given timing tion engine transforms a design creating additional infor- constraints is critical. At the end of a design flow, if mation for the design and ensuring that timing, power, thefinallayoutofacircuitisabletomeetthegiven area, testability, and other design constraints are met. timing constraints, then timing closure is said to be attained [1–4]. In this paper, we review the basics of timing closure problem and explain the difficulty in achieving it. Fur- A design flow as shown in Figure 1(a)isanarduouspro- thermore, we describe traditional techniques that are cess and requires a huge amount of effort from designers employed to ameliorate the problem of timing closure [3,5]. The defined targets and the strategies employed and highlight their inadequacies at advanced process to attain timing closure decide the time taken to signoff nodes. The problem of timing closure becomes more © 2018 IETE 2S.SAURABHET AL.: TIMING CLOSURE PROBLEM Figure 1: (a) Steps involved in a typical design process or design flow. (b) Interaction between design database, analysis engine and implementation engine difficult at advanced process nodes due to: (a) increased example, in the gate-based netlist, there is no infor- complexity of designs (b) new device phenomenon, and mation about the nature of interconnects. There- (c) lower supply voltages (VDD), higher clock-speed and fore, implementation engines that operate on a gate- increased impact of process variations tighten timing basednetlistareforcedtoestimateinterconnect constraints. Furthermore, we review techniques that can delay using some heuristics. However, the estimated be applied to ease timing closure problem at advanced delay can be widely different from the actual delay process nodes. It is important to point out that, in this computed in the later stages of a design flow [2, 3]. As paper, by advanced process nodes we mean “14-nm” a result, actual timing violations are discovered only onward technology nodes. Therefore, this review will in later stages and creates timing closure problems. also help VLSI designers and researchers in appreciating Furthermore, timing closure problem is aggravated impending challenges of future technology nodes. by the fact that, during later stages of a design flow, the flexibility to make changes in a design decreases. The rest of this paper is organized as follows. In Section 2, For example, after detailed routing, it is difficult to do we explain the basics of timing closure problem. In Sec- logic optimization since some new cells can be cre- tions 3 and 4, we highlight challenges of timing closure ated/destroyed which would entail repeating certain at advanced process nodes and possible solutions. In physical design steps such as placement and routing. Section 5,wemakeconcludingremarks. (2) Conflict among timing and other metrics of a design: The design process involves considering sev- eral parameters such as timing, area, power, signal 2. THE PROBLEM integrity, reliability, etc. In general, some of these The problem of timing closure becomes difficult due to parameters such as power and area are in conflict the following characteristics of design processes: with the timing of a circuit. Therefore, when an implementation engine improves power or area of (1) High level of abstraction in the early phases of a acircuit,thenthetimingdegrades.Furthermore, design: During early phases of a design, the level of the problem is complicated by the fact that, in the abstractionishighandthereislessinformationcon- early phases of a design, the timing-critical portion tent in the design, as illustrated in Figure 2(a). For ofadesignisnotexactlyknown.Therefore,even S. SAURABH ET AL.: TIMING CLOSURE PROBLEM 3 Figure 2: (a) Information content increases and flexibility to make change decreases, as a design flow proceeds. (b) A design flow becomes iterative when decisions of preceding steps need to be reverted in the timing-critical portion of a circuit an imple- better timing during early stages of a design flow, mentation engine can choose to trade-off timing thus mitigating the timing closure problem. The dif- and improve other parameters of the circuit such as ficulty in finding actual timing-critical portion of power, area, testability, reliability, etc. This exacer- a circuit during early phases of a design flow is bates the problem of timing closure. handled by taking a pessimistic view of the design attributes such as wire-delay or by putting additional The above-mentioned characteristics of design processes timing margins [2,6,7]. These strategies compensate make a design flow iterative and it can never be guaran- the lack of information in early phases of a design teed that a design flow will finally converge3 [ ]. As an flow by over-designing, which often results in an illustration, assume that for a given design, it is found increased area and power [2]. after detailed routing that many of the violating paths (2) Predict and prevent: One of the strategies to mit- pass through a particular ripple-carry adder (RCA). One igate timing closure problem is by predicting the of the techniques to fix this problem can be to change timing problems early in a design flow and taking thearchitectureoftheadderfromRCAtocarrylook- preventive measures to avoid them [8,9]. This strat- ahead(CLA).Thiswillrequirechangingadecisionmade egy can be implemented in various ways depend- during RTL synthesis, as shown in Figure 2(b). Chang- ing on the information content of a design [2,8,9]. ing an RCA to CLA can result in an increased number For example, logic synthesis can take its decisions of cells, which can force displacement and re-routing of based on estimated interconnect delays