80C186XL/80C188XL 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS Y Low Power, Fully Static Versions of Y Completely Object Code Compatible 80C186/80C188 with Existing 8086/8088 Software and Has 10 Additional Instructions over Y Operation Modes: Ð Enhanced Mode 8086/8088 Ð DRAM Refresh Control Unit Y Speed Versions Available Ð Power-Save Mode Ð 25 MHz (80C186XL25/80C188XL25) Ð Direct Interface to 80C187 Ð 20 MHz (80C186XL20/80C188XL20) (80C186XL Only) Ð 12 MHz (80C186XL12/80C188XL12) Ð Compatible Mode Y Direct Addressing Capability to Ð NMOS 80186/80188 Pin-for-Pin 1 MByte Memory and 64 Kbyte I/O Replacement for Non-Numerics Applications Y Available in 68-Pin: Ð Plastic Leaded Chip Carrier (PLCC) Y Integrated Feature Set Ð Ceramic Pin Grid Array (PGA) Ð Static, Modular CPU Ð Ceramic Leadless Chip Carrier Ð Clock Generator (JEDEC A Package) Ð 2 Independent DMA Channels Ð Programmable Interrupt Controller Y Available in 80-Pin: Ð 3 Programmable 16-Bit Timers Ð Quad Flat Pack (EIAJ) Ð Dynamic RAM Refresh Control Unit Ð Shrink Quad Flat Pack (SGFP) Ð Programmable Memory and Y Available in Extended Temperature Peripheral Chip Select Logic Range (b40§Ctoa85§C) Ð Programmable Wait State Generator Ð Local Bus Controller Ð Power-Save Mode Ð System-Level Testing Support (High Impedance Test Mode) The Intel 80C186XL is a Modular Core re-implementation of the 80C186 microprocessor. It offers higher speed and lower power consumption than the standard 80C186 but maintains 100% clock-for-clock functional com- patibility. Packaging and pinout are also identical. 272431-1 *Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. October 1995 Order Number: 272431-004 © COPYRIGHT INTEL CORPORATION, 1995 1 80C186XL/80C188XL 16-Bit High-Integration Embedded Processors CONTENTS PAGE CONTENTS PAGE INTRODUCTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4 AC SPECIFICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 24 Major Cycle Timings (Read Cycle) ÀÀÀÀÀÀÀÀÀ 24 80C186XL CORE ARCHITECTURE ÀÀÀÀÀÀÀÀ 4 Major Cycle Timings (Write Cycle) ÀÀÀÀÀÀÀÀÀ 26 80C186XL Clock Generator ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4 Major Cycle Timings (Interrupt Bus Interface Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5 Acknowledge Cycle) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 27 80C186XL PERIPHERAL Software Halt Cycle Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 28 ARCHITECTURE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5 Clock Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 29 Chip-Select/Ready Generation Logic ÀÀÀÀÀÀÀ 5 Ready, Peripheral and Queue Status DMA Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6 Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 30 Timer/Counter Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6 Reset and Hold/HLDA Timings ÀÀÀÀÀÀÀÀÀÀÀÀ 31 Interrupt Control Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6 AC TIMING WAVEFORMS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 36 Enhanced Mode Operation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6 AC CHARACTERISTICS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 37 Queue-Status Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6 DRAM Refresh Control Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7 EXPLANATION OF THE AC Power-Save Control ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7 SYMBOLS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 39 Interface for 80C187 Math Coprocessor DERATING CURVES ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 40 (80C186XL Only) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7 ONCE Test Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7 80C186XL/80C188XL EXPRESS ÀÀÀÀÀÀÀÀÀ 41 PACKAGE INFORMATION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8 80C186XL/80C188XL EXECUTION TIMINGS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 41 Pin Descriptions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8 80C186XL/80C188XL Pinout INSTRUCTION SET SUMMARY ÀÀÀÀÀÀÀÀÀÀ 42 Diagrams ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 16 REVISION HISTORY ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 48 ELECTRICAL SPECIFICATIONS ÀÀÀÀÀÀÀÀÀ 22 ERRATA ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 48 Absolute Maximum Ratings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22 PRODUCT IDENTIFICATION ÀÀÀÀÀÀÀÀÀÀÀÀÀ 48 DC SPECIFICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22 Power Supply Current ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 23 2 2 80C186XL/80C188XL 272431±2 NOTE: Pin names in parentheses applies to 80C188XL. Figure 1. 80C186XL/80C188XL Block Diagram 3 3 80C186XL/80C188XL (2a) 272431±3 272431±4 (2b) Note 1: XTAL Frequency L1 Value 20 MHz 12.0 mH g20% 25 MHz 8.2 mH g20% 32 MHz 4.7 mH g20% 40 MHz 3.0 mH g20% LC network is only required when using a third overtone crystal. Figure 2. Oscillator Configurations (see text) INTRODUCTION The 80C186XL oscillator circuit is designed to be used either with a parallel resonant fundamental or Unless specifically noted, all references to the third-overtone mode crystal, depending upon the 80C186XL apply to the 80C188XL. References to frequency range of the application. This is used as pins that differ between the 80C186XL and the the time base for the 80C186XL. 80C188XL are given in parentheses. The output of the oscillator is not directly available The following Functional Description describes the outside the 80C186XL. The recommended crystal base architecture of the 80C186XL. The 80C186XL configuration is shown in Figure 2b. When used in is a very high integration 16-bit microprocessor. It third-overtone mode, the tank circuit is recommend- combines 15±20 of the most common microproces- ed for stable operation. Alternately, the oscillator sor system components onto one chip. The may be driven from an external source as shown in 80C186XL is object code compatible with the Figure 2a. 8086/8088 microprocessors and adds 10 new in- struction types to the 8086/8088 instruction set. The crystal or clock frequency chosen must be twice the required processor operating frequency due to The 80C186XL has two major modes of operation, the internal divide by two counter. This counter is Compatible and Enhanced. In Compatible Mode the used to drive all internal phase clocks and the exter- 80C186XL is completely compatible with NMOS nal CLKOUT signal. CLKOUT is a 50% duty cycle 80186, with the exception of 8087 support. The En- processor clock and can be used to drive other sys- hanced mode adds three new features to the system tem components. All AC Timings are referenced to design. These are Power-Save control, Dynamic CLKOUT. RAM refresh, and an asynchronous Numerics Co- processor interface (80C186XL only). Intel recommends the following values for crystal se- lection parameters. 80C186XL CORE ARCHITECTURE Temperature Range: Application Specific ESR (Equivalent Series Resistance): 60X max 80C186XL Clock Generator C0 (Shunt Capacitance of Crystal): 7.0 pF max C1 (Load Capacitance): 20 pF g2pF The 80C186XL provides an on-chip clock generator Drive Level: 2 mW max for both internal and external clock generation. The clock generator features a crystal oscillator, a divide- by-two counter, synchronous and asynchronous ready inputs, and reset circuitry. 4 4 80C186XL/80C188XL Bus Interface Unit spond to bus cycles. An offset map of the 256-byte control register block is shown in Figure 3. The 80C186XL provides a local bus controller to generate the local bus control signals. In addition, it employs a HOLD/HLDA protocol for relinquishing Chip-Select/Ready Generation Logic the local bus to other bus masters. It also provides outputs that can be used to enable external buffers The 80C186XL contains logic which provides and to direct the flow of data on and off the local programmable chip-select generation for both mem- bus. ories and peripherals. In addition, it can be programmed to provide READY (or WAIT state) gen- The bus controller is responsible for generating 20 eration. It can also provide latched address bits A1 bits of address, read and write strobes, bus cycle and A2. The chip-select lines are active for all mem- status information and data (for write operations) in- ory and I/O cycles in their programmed areas, formation. It is also responsible for reading data whether they be generated by the CPU or by the from the local bus during a read operation. Synchro- integrated DMA unit. nous and asynchronous ready input pins are provid- ed to extend a bus cycle beyond the minimum four The 80C186XL provides 6 memory chip select out- states (clocks). puts for 3 address areas; upper memory, lower memory, and midrange memory. One each is provid- The 80C186XL bus controller also generates two ed for upper memory and lower memory, while four control signals (DEN and DT/R) when interfacing to are provided for midrange memory. external transceiver chips. This capability allows the addition of transceivers for simple buffering of the OFFSET multiplexed address/data bus. Relocation Register FEH During RESET the local bus controller will perform the following action: DAH # Drive DEN,RDand WR HIGH for one clock cy- DMA Descriptors Channel 1 cle, then float them. D0H # Drive S0±S2 to the inactive state (all HIGH) and then float. CAH DMA Descriptors Channel 0 # Drive LOCK HIGH and then float. C0H # Float AD0±15 (AD0±8), A16±19 (A9±A19), BHE (RFSH), DT/R. A8H Drive ALE LOW Chip-Select Control Registers # A0H # Drive HLDA LOW. RD/QSMD, UCS, LCS, MCS0/PEREQ, MCS1/ 66H Time 2 Control Registers ERROR and TEST/BUSY pins have internal pullup 60H devices which are active while RES is applied. Ex- 5EH cessive loading or grounding certain of these pins Time 1 Control Registers causes the 80C186XL to enter an alternative mode 58H of operation: 56H Time 0 Control Registers # RD/QSMD low results in Queue Status Mode. 50H