Europaisches Patentamt J» European Patent Office Publication number: 0166 772 Office europeen des brevets B1 EUROPEAN PATENT SPECIFICATION (45) Date of publication of patent specification: 21.03.90 int. ci.5: G 06 F 9/30, G 06 F 5/00 ® Application number: 85900484.8 (§) Date of filing: 20.12.84 (§) International application number: PCT/GB84/00446 (§) International publication number: WO 85/02922 04.07.85 Gazette 85/15 IMPROVEMENTS IN OR RELATING TO COMPUTER SYSTEMS. (M) Priority: 21.12.83 GB 8334079 Proprietor: HEMDAL, Goran Anders Henrik 46 St. Leonards Court St. Leonards Road London SW14 7NQ (GB) Date of publication of application: 08.01.86 Bulletin 86/02 Inventor: HEMDAL, Goran Anders Henrik 46 St. Leonards Court St. Leonards Road Publication of the grant of the patent: London SW14 7NQ (GB) 21.03.90 Bulletin 90/12 @ Representative: Bayliss, Geoffrey Cyril et al Designated Contracting States: BOULT, WADE & TENNANT 27 Furnival Street AT BE CH DE FR GB LI LU NL SE London EC4A1PQ(GB) References cited: US-A-3 930232 US-A-3 945 002 Computer Architecture News, Volume 9, no. 4, 15 June 1981, New York (US) D.D.Hill: 'A Hardware Mechanism for supporting Range CM Checks', pages 15-21. Note: Within nine months from the publication of the mention of the grant of the European notice to the patent, any person may give European Patent Office of opposition to the European patent granted. Notice of opposition shall '" reasoned statement. It shall not be deemed ■1 ln LT,"!" to have been filed until the opposition fee has been LU paid. (Art. 99(1) European patent convention). Courier Press, Leamington Spa, England. EP 0166 772 B1 Description This invention relates to computer systems and the general object of the invention is to increase the capacity and software security of binary computers by means of logic circuitry, which is interposed s between a standard CPU, (such as one represented by Motorola MC68000, INTEL 80286 etc), and the memory accessed from this CPU. Computer Architecture News. Volume 9, No. 4, 15 June 1981, New York, Pages 15 — 21 discloses a computer system having a central processing unit, a main memory for storage of information in binary form and a master control unit for individual and selected checking of value ranges of data elements to be io written into or read from the main memory, wherein arithmetic circuits interposed in the data part path between the central processing unit and the main memory generate an interrupt signal for the central processing unit in the case of an out-of-range value being detected. The invention provides a computer system having a central processing unit, a main memory for storage of information in binary form, a master control unit having means for performing individual and 15 selective checking of value ranges of data elements to be written into or read from the main memory, and having means for generating an interrupt signal to the central processing unit in the case of an out-of-range value being detected, and arithmetic circuit means interposed in the data path to and from the main memory for performing arithmetic functions on data read to or from the main memory; wherein the master control unit has a memory containing a data descriptor table with a table entry for each individually 20 accessible data element in the main memory, with two elements of each descriptor table entry assigned for range check and conversion purposes, means for determining one of the extreme limits of the value range of the data element in the main memory associated with the data descriptor table entry in accordance with one of the elements, and means for determining the number of values in the value range of the associated data element in accordance with the second of the elements, whereby the arithmetic circuits, responsive to 25 each read operation, to the data element received from main memory and to the associated Data Descriptor Table-elements, convert the physical value of the data element received from main memory, in dependence on said one extreme limit of the value range, to a logical value and deliver said logical value to the central processing unit and that the arithmetic circuits, responsive to each write operation, to the data element received from the central processing unit and to the associated Data Descriptor Table-elements, 30 convert the logical value of the data element received from the central processing unit, in dependence on said one extreme limit of the value range, to a physical value and check said physical value by comparing it with said number of values in the value range before said physical value can be delivered to the main memory. The invention thus allows range checks, and conversions which otherwise would have to be explicitly 35 coded into a programme to be performed automatically, thereby reducing the code volumes and permitting faster execution. The invention also raises the software security within the computer because there is no way that the programmer can forget to perform, or deliberately omit, the range checks and conversions in order to speed up the execution of a programme. Computers conventionally operate in binary mode, i.e. information is stored and treated in binary "0 form. This is illustrated by Figures 1, 2 and 3. Figure 1 shows a typical binary computer consisting of a Central Processing Unit (CPU) and a Main Memory (M). The CPU is connected to M via an Address Bus (ABUS) with k address bits, a Data Bus (DBUS) with 16 data bits and two control connections (R and W). The number of data bits on the data bus corresponds with the Word Length of the Main Memory (M), i.e. the number of data bits in each memory word, which in this example is assumed to be 16 bits. Each 45 memory word can therefore store 216=65536 different values. The number of address bits on the Address Bus (K) defines the number of addressable memory words which is 2k. The address of each of these words is defined by the corresponding values 0.1 ... 2k~1. The CPU consists of a number of elements of which the most important for the purpose of this description are the Micro Program Unit (MPU), the Arithmetic-Logic Unit (ALU), the Address Register (AR), 50 the Data Register (DR) and the Carry Register (C). The MPU controls the transfer of information between the various registers of the CPU and the main memory M. If for instance the contents of the Memory Word at address X are to be transferred to the Data Register DR, the MPU would first transfer the value X from MPU itself to the Address Register (AR) via the Data Bus (DBUS) by applying the appropriate Control Signals (All Control Signals in Figure 1 are indicated 55 by solid black arrows). Once the value X is contained in AR, the corresponding word in the main memory is now indicated. By applying the Read Control Signal (R) to the memory the contents of this memory word is read to the Data Bus and can thereby be gated into DR. When writing into memory the data would be drawn from DR onto the Data Bus and written into the corresponding memory word by application of the Write Control Signal (W). so Information is stored and processed in binary form, whereby a data word with N bits is able to store 2N different values. Figure 2 illustrates the different values which may be stored in a data word where N=4 and several possible representations of these values. In representation A the actual value may be directly calculated from the corresponding bit position, e.g. the binary value 1011 represents the actual value: 65 23*1+22*O + 21*1+2°*1=8 + 2+1 = 11 EP 0166 772 B1 In representation B the most significant bit is used as a sign bit with the actual value given by the remaining bits. For positive values the value is calculated as in representation A. For negative values the so called 2:s complement is used, i.e. the value is (the value of representation A) — 16. Thus, in this case the value 1011 represents the actual value: 5 23 * 1 + 22 * O + 21 * 1 + 2° * 1 - 16 (23 = 1) = 8 + 2 + 1 - 16 = -5. In representation C, only the values 0011 ... 1100 are used to represent the values 0—9 with 6 of all possible 16 values unused. Figure 3 illustrates a typical example of an arithmetic operation performed by jo ALU in Figure 1 . The operation performed is a binary addition, whereby it is assumed that the operands to be added have been transported to two registers within ALU (IR1 and IR2) both of which contains N data bits. The contents of the two registers IR1 and IR2 are added and the result transferred to a result register (OR) with N + 1 data bits, of which bit(N + 1) is transferred to the Carry Flag (C) and the N least significant bits of the result transferred out on the data bus DBUS. If, for instance, representation A of Figure 2 is used ?5 and the values 5 and 7 are to be added, then: 5 => 0101 + 7 => + 0111 Result => 0 1100 => 12 with NO CARRY 20 (CARRY) In this (carry) case the result is greater than can arithmetically correct result. If, as a second example, the values 7 and 11 are to be added, then: 7=> 0111 25 + 11 => + 1011 Result => 1 0010 = 2 with CARRY (carry) In this (carry) case the result is greater than what can be represented by 4 bits, i.e.