FULLY-INTEGRATED CMOS SWITCHED-CAPACITOR BUCK CONVERTER USING THREE SWITCHING NETWORKS FOR HIGH EFFICIENCY OVER A WIDE RANGE OF LINE VOLTAGE BY MUHAMMED JUNAYET HOSSAIN, B.Tech A dissertation submitted to the Graduate School in partial fulfillment of the requirements for the degree Master of Sciences, Engineering Specialization in: Electrical Engineering New Mexico State University Las Cruces, New Mexico September 2014 \FULLY-INTEGRATED CMOS SWITCHED-CAPACITOR BUCK CONVERTER USING THREE SWITCHING NETWORKS FOR HIGH EFFICIENCY OVER A WIDE RANGE OF LINE VOLTAGE," a dissertation prepared by MUHAMMED JUNAYET HOSSAIN in partial fulfillment of the requirements for the degree, Master of Sciences has been approved and accepted by the following: Dr. Loui Reyes Associate Dean of the Graduate School Chair of the Examining Committee Date Committee in charge: Dr. Paul M. Furth, Associate Professor, Chair. Dr. Wei Tang, Assistant Professor. Dr. Abbas Ghassemi, Professor. ii DEDICATION Dedicated to my mother Marzina Begum, father Zahid Hossain, my wife Moushumi Akter and my advisor Dr. Paul Furth. iii ACKNOWLEDGMENTS I am grateful to my parents Marzina Begum and Muhammed Zahid Hossain for not only allowing me to pursue high education but also for supporting me in my completion of my Master's degree. I respect their sacrifice. I would like to thank my wife Mousumi Akter Sinthia for taking care of me during this rigorous endeavor. Without her love and compassion, I could not have accomplished what I did. I would like to show my gratitude to Dr. Paul M. Furth for advising me throughout my Master's degree. I learned incredible amount from his teach- ing through courses like digital VLSI and Integrated Power Management. From working alongside him, I was able to cultivate a strong research philosophy and practices. His supportive behavior was essential in helping me to achieve my goal. When I faced with overwhelming complication in the research, he even took the time to pray with me to calm my anxiety. From the beginning, I enjoyed our delightful discussions. Also his wife, Carol, was cordial to me and my wife, she helped us adjust to any difficult situation that arose. I am trully grateful to Dr. Gary A. Eiceman, Dr. Greg Fant, Prof. Lynn Kelly, Dr. Vimal Chaitanya and Dr. Susie Bussmann to give me job opportunities during my Master's as well as I had very nice time while working with them. I would like to thank Dr. Wei Tang and Dr. Abbas Ghassemi for accepting my request to be the thesis committee members. iv I appreciate Dr. Jaime Ramirez for teaching us analog and mixed-signal concepts. He is dedicate to deliver his knowledge to enlighten us throughout the semesters. One true friend, Andre Bergsagel, who helped me in each step of the last two years that I will not forget in future. He is one of the best person that I have met after coming aboard. I would like to specially thank Anurag Veerabathini who helped me a lot by discussing about our research. I want to thank Z. M. Saifullah Amil, Mohammad Atiqul Haque, SriHarsh Pakala, Alejandro Romn Loera, Bala Kesava, Yeshwanth Puppala, Venkat Harish Nammi. They inspired me to complete my research and made my life more colorful. v VITA Born in Dhaka, Bangladesh . Education 2003 - 2007 B.Tech. Electrical and Electronic Engineering, Khulna University of Engineering and Technology , Bangladesh 20012 - 2014 MSEE. in Electrical Engineering, New Mexico State University, USA Awards and Achievments 2012 - 2013 International Out-of-State Alumni Scholarship, NMSU,USA. Experience Teaching Assistant, Electrical Engineering, SDSMT, Spring-2012 1. Assist students in the labs and in the projects for Signal and System Research Assistant, Chemistry and Bio-chemistry, NMSU, Spring-2013 1. Modified Schematic and PCB Design of High voltage (1:5 kV-3:5 kV) and high frequency (5 MHz-25 MHz) pulse generator circuits for an IMS project. Research Assistant, Engineering Technology, NMSU, Fall-2013 1. Developed FPGA lab using VHDL, C and Assemble Language in Altera DE board. vi ABSTRACT FULLY-INTEGRATED CMOS SWITCHED-CAPACITOR BUCK CONVERTER USING THREE SWITCHING NETWORKS FOR HIGH EFFICIENCY OVER A WIDE RANGE OF LINE VOLTAGE BY MUHAMMED JUNAYET HOSSAIN, B.Tech Master of Sciences, Engineering Specialization in Electrical Engineering New Mexico State University Las Cruces, New Mexico, 2014 Dr. Paul M. Furth, Chair A fully-integrated switched-capacitor DC-DC buck converter is designed in 0:5 µm CMOS process for low line regulation from 2:5 VDC to 4:5 VDC that converts to an output voltage of 1:2 ± 0:15 V. This integrated system achieves a maximum efficiency of 70%. The total integrated capacitance is 1:6 nF and the ripple of the output voltage varies from 30 mV to 93 mV. The entire sys- tem is built up using transfer capacitors, NMOS capacitor as the load capacitor, CMOS switches, clocked-comparators, various logic gates with driver cells, a clock generator and voltage dividers. The load current is fixed at 3 mA. vii To achieve low line regulation, three switching networks (2 : 1; 5 : 2; and 3 : 1) are implemented in the system. A multi-layer technique is applied to the lay- out of the transfer capacitors that helps to reduce parasitic capacitances, thereby improving converter efficiency, and achieve smaller size. viii TABLE OF CONTENTS LIST OF TABLES xii LIST OF FIGURES xiv 1 INTRODUCTION 1 1.1 Switched-Capacitor . 1 1.2 Unique Contributions of this Thesis . 3 1.3 Thesis Organization . 3 2 LITERATURE REVIEW 4 2.1 Integrated DC-DC Converter . 4 2.2 Low Drop-Output (LDO) Regulator . 5 2.3 Inductor-based Switching Regulator . 7 2.4 Switched-Capacitor DC-DC Converter . 10 2.4.1 Switched-Capacitor Resistor . 10 2.4.2 Design Topologies . 12 2.4.3 Output ripple of SC converters . 13 2.4.4 Power Losses and Efficiency . 16 2.5 Clocked Comparator . 17 2.6 Non-overlapping Clock Generator . 18 2.7 Controller Design for Line Regulation . 21 ix 3 DESIGN AND SIMULATIONS 24 3.1 Parasitic Capacitance . 24 3.2 Specifications of SC buck converters . 26 3.3 Switched Capacitor (SC) of 2 : 1 Buck Converter . 28 3.3.1 Design of 2 : 1 SC Buck Converter . 28 3.3.2 Simulation of 2 : 1 SC Buck Converter . 30 3.3.3 Analysis of 2 : 1 SC Buck Converter . 32 3.4 Switched Capacitor (SC) of 3 : 1 Buck Converter . 39 3.4.1 Design of 3 : 1 SC Buck Converter . 40 3.4.2 Simulation of 3 : 1 SC Buck Converter . 40 3.4.3 Analysis of 3 : 1 SC Buck Converter . 44 3.5 Switched Capacitor (SC) of 5 : 2 Buck Converter . 49 3.5.1 Design of 5 : 2 SC Buck Converter . 49 3.5.2 Simulation results of 5 : 2 SC Buck Converter . 50 3.6 Non-overlapping Clock Generator . 51 3.7 Clocked Comparator . 55 3.8 Logic Gates and Driver Cells . 58 3.9 Integrated System . 63 3.9.1 Design of Integrated System . 63 3.9.2 Simulation Results of Integrated SC Buck Converter . 64 3.9.3 Line regulation . 69 4 EXPERIMENTAL RESULTS 72 4.1 Layout . 72 4.1.1 Layout of Capacitors and Resistors . 72 4.1.2 Layout of Controller Components and Switches . 75 x 4.1.3 Layout of Integrated System . 81 4.2 Hardware Test Results . 83 4.2.1 Test result of the clock generator . 83 4.2.2 Test result of the Clocked Comparator . 83 4.2.3 Test result of the integrated system . 86 4.2.4 Line transient . 88 4.2.5 Line regulation and efficiency . 92 5 DISCUSSION AND CONCLUSION 97 5.1 Simulation vs Test Results . 97 5.2 Comparison between Other Published Works . 99 5.3 High Ripple for ESR in the Capacitors . 100 5.4 Design of Control Loop . 103 5.5 Noise from the Environment . 104 5.6 Future Work . 104 APPENDICES 109 A. Test Document 110 B. C5 Process Parameters 127 REFERENCES 130 xi LIST OF TABLES 1.1 Comparison of different DC-DC converters [3] . 2 3.1 2 : 1 SC buck converter specifications . 27 3.2 Switch sizes for 2 : 1 SC buck converter . 30 3.3 Optimum switch sizes for 3 : 1 SC buck converter . 40 3.4 Optimum switch sizes for 5 : 2 SC buck converter . 51 3.5 Switch sizes for clocked-comparator . 56 3.6 Clock phases from Logic gates in different SC networks . 60 3.7 The transfer and load capacitor selection for the integrated system 64 3.8 Switch sizes for clocked-comparator . 66 3.9 Integrated System Results . 66 4.1 The area of switches . 81 4.2 Measured values of Efficiency and Ripple at different input voltages 93 5.1 Mismatch between the simulation and test results . 98 5.2 Comparison with recently published fully integrated SC buck con- verters . 99 1 Pin Description Table of the Integrated Circuit . 112 2 Selection of clock voltage & offset in different input voltage . 117 3 Comparator Output in different SC network . 117 xii 4 Clock phases from Logic gates in different SC network . 119 5 Power and Efficiency Calculation of SC converter . 123 xiii LIST OF FIGURES 2.1 Block diagram of low drop-output (LDO) regulator. [4] . 5 2.2 Block diagram of switching buck converter [6] . 8 2.3 Output voltage waveform of VS(t) [6] . 8 2.4 Architecture of LC filter and SPDT in a switching converter [6] . 9 2.5 (a) Switched-capacitor circuit, (b) equivalent resistor of SC, (c) the equivalent circuit during φ1 and (d) the equivalent circuit during φ2 [2] .