USO0953673OB2 (12) United States Patent (10) Patent No.: US 9,536,730 B2 Lee et al. (45) Date of Patent: Jan. 3, 2017 (54) CLEANING FORMULATIONS 7/3209 (2013.01): CIID 7/3218 (2013.01); CIID 7/3281 (2013.01); CIID 7/5013 (71) Applicant: AIR PRODUCTS AND CHEMICALS (2013.01); CIID 7/5022 (2013.01); G03F INC. Allentown, PA (US) 7/425 (2013.01); G03F 7/426 (2013.01) (58) Field of Classification Search (72) Inventors: Yi Chia Lee, Dansheui (TW); CPC ............................... C11D 11/0047; C11D 7/50 Madhukar Bhaskara Rao, Fogelsville, See application file for complete search history. PA (US); Gautam Banerjee, Latham, NY (US); Wen Dar Liu, Chupei (TW); Aiping Wu, Macungie, PA (US); Seiji (56) References Cited Inaoka, Midland, MI (US) U.S. PATENT DOCUMENTS Assignee: AIR PRODUCTS AND (73) 5,279,771 A 1/1994 Lee CHEMICALS, INC., Allentown, PA 5,417,877 A 5, 1995 Ward (US) 5,746,837 A 5/1998 Becket al. 6,117,783 A 9, 2000 Small et al. (*) Notice: Subject to any disclaimer, the term of this 6,248,704 B1 6/2001 Small et al. patent is extended or adjusted under 35 (Continued) U.S.C. 154(b) by 392 days. FOREIGN PATENT DOCUMENTS (21) Appl. No.: 14/010,748 EP O 647 884 A1 4f1995 (22) Filed: Aug. 27, 2013 EP 1736534 A1 12/2006 (Continued) (65) Prior Publication Data Primary Examiner — Gregory Webb US 2014/O109931 A1 Apr. 24, 2014 (74) Attorney, Agent, or Firm — Anne B. Kiernan; Joseph Related U.S. Application Data D. Rossi (60) Provisional application No. 61/717,152, filed on Oct. 23, 2012, provisional application No. 61/817,134, (57) ABSTRACT filed on Apr. 29, 2013. A composition and method for removing copper-containing post-etch and/or post-ash residue from patterned microelec (51) Int. C. tronic devices is described. The removal composition CLID 7/50 (2006.01) includes water, a water-miscible organic solvent, an amine HOIL 2L/02 (2006.01) compound, an organic acid, and a fluoride ion source. The CLID 7/10 (2006.01) compositions effectively remove the copper-containing CLID 7/26 (2006.01) post-etch residue from the microelectronic device without CLID 7/32 (2006.01) damaging exposed low-k dielectric and metal interconnect GO3F 7/42 (2006.01) materials. (52) U.S. C. CPC ........... HOIL 21/02052 (2013.01): CIID 7/10 (2013.01); CIID 7/265 (2013.01): CIID 21 Claims, 1 Drawing Sheet Before Clean 950 (25C, 1min) Sidewal (a) (c) Top surface (d) US 9,536,730 B2 Page 2 (56) References Cited 2007/0078073 A1 4/2007 Auger 2007/0179072 A1* 8, 2007 Rao .......................... C11D 7/08 U.S. PATENT DOCUMENTS 51Of 175 2008/O139436 A1* 6/2008 Reid ...................... C11D 3/044 6,326,130 B1 12/2001 Schwartzkopf et al. 510, 176 6,749,998 B2 6/2004 Schwartzkopfet al. 2008. O169004 A1* 7, 2008 Wu .......................... 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CID, 2003/0078173 A1 4/2003 Wojtczak et al. 2003/O130149 A1* 7/2003 Zhou .................... C11D 7,3218 2010.0152086 Al 6 2010 Wu et al. 510, 176 2010, 0163788 A1 7/2010 Visintin et al. 2003/0181342 A1* 9/2003 Seijo ...................... C11D 7.265 2011/0117751 A1 5, 2011 Sonthalia et al. 51Of 175 2012/0048295 A1 3/2012 Du ....................... C11D 7/3245 2004, OO18949 A1 1/2004 Lee 134/3 2004/0038840 A1 2/2004 Lee ...................... C11D 3,0073 510,202 FOREIGN PATENT DOCUMENTS 2004/0171503 A1 9, 2004 Rowto et al. 2004/O220065 A1 11, 2004 HSu EP 1813667 A1 8, 2007 2005, OO14667 A1 1/2005 Aoyama et al. EP 2500407 A1 9, 2012 2005/0090416 A1* 4/2005 Lee .......................... C11D 3A30 JP 2005522O27 7/2005 51Of 175 JP 2005528660 9, 2005 2005/0187118 A1* 8/2005 Haraguchi ............... C11D 7/10 JP 2005532691 10/2005 51Of 175 JP 2008198994 8, 2006 2005/0215446 A1 9/2005 Wojtczak et al. JP 2008277718 11/2008 2006/0016785 A1 1/2006 Egbe et al. JP 2010147476 T 2010 2006/0178282 A1 8/2006 Suyama et al. WO 2006110645 A2 10, 2006 2006/0237392 A1 10/2006 Auger et al. WO 2006129549 12/2006 2006/0270573 A1 11/2006 Ikemoto et al. WO 2009073588 A1 6, 2009 2006/0293208 A1* 12/2006 Egbe .................... C11D 7.3263 510.407 * cited by examiner U.S. Patent Jan. 3, 2017 US 9,536,730 B2 3 s ss 3. CO S. ar US 9,536,730 B2 1. 2 CLEANING FORMULATIONS interconnect wiring, reactive ion etching (RIE) is used to produce vias through the interlayer dielectric to provide CROSS-REFERENCE TO RELATED contact between one level of silicon, silicide or metal wiring APPLICATIONS to the next level of wiring. These vias typically expose, Al, AlCu, Cu, Ti, TiN, Ta, TaN, silicon or a silicide such as, for This nonprovisional application claims the benefit of U.S. example, a silicide of tungsten, titanium or cobalt. The RIE Application No. 61/717,152, filed on Oct. 23, 2012, and U.S. process, for example, leaves a residue on the involved Application No. 61/817,134, filed on Apr. 29, 2013, both Substrate comprising a complex mixture that may include, provisional applications having the same title as the present for example, re-sputtered oxide material, polymeric material application. U.S. Application Nos. 61/717,152 and 61/817, 10 derived from the etch gas, and organic material from the 134 are hereby incorporated by reference in their entireties. resist used to delineate the vias. Additionally, following the termination of the etching BACKGROUND OF THE INVENTION step, the photoresist and etch residues must be removed from the protected area of the wafer so that the final finishing The present invention relates to cleaning compositions 15 operation can take place. This can be accomplished in a that can be used for a variety of applications including, for plasma “ashing step by the use of Suitable plasma ashing example, removing unwanted resist films, post-etch, and gases. This typically occurs at high temperatures, for post-ash residue on a semiconductor Substrate. In particular, example, above 200° C. Ashing converts most of the organic the present invention relates to cleaning compositions useful residues to volatile species, but leaves behind on the sub for the removal of residue, preferably copper-containing strate a predominantly inorganic residue. Such residue typi post-etch and/or post-ash residue, from the Surface of Sub cally remains not only on the surface of the substrate, but strates, preferably microelectronic devices, and methods of also on the inside walls of Vias that may be present. As a using said compositions for removal of same. result, ash-treated Substrates are often treated with a cleaning The background of the present invention will be described composition typically referred to as a “liquid stripping in connection with its use in cleaning applications involving 25 composition' to remove the highly adherent residue from the manufacture of integrated circuits. It should be under the Substrate. Finding a suitable cleaning composition for stood, however, that the use of the present invention has removal of this residue without adversely affecting, e.g., wider applicability as described hereinafter. corroding, dissolving or dulling, the metal circuitry has also In the manufacture of integrated circuits, it is sometimes proven problematic. Failure to completely remove or neu necessary to etch openings or other geometries in a thin film 30 tralize the residue can result in discontinuances in the deposited or grown on the Surface of silicon, gallium circuitry wiring and undesirable increases in electrical resis arsenide, glass, or other substrate located on an in-process tance. integrated circuit wafer. Present methods for etching Such a Cleaning of post-etch residues remains a critical process film require that the film be exposed to a chemical etching step for any low-k dielectric material to Succeed. As the agent to remove portions of the film. The particular etching 35 dielectric constant of the low-k material pushes below 2.4. agent used to remove the portions of the film depends upon the chemical and mechanical sensitivity increases (e.g., the nature of the film. In the case of an oxide film, for chemical strength decreases, etc.), thereby requiring shorter example, the etching agent may be hydrofluoric acid. In the process times and/or less aggressive chemistries. Unfortu case of a polysilicon film, it will typically be hydrofluoric nately, shorter process times generally translates to more acid or a mixture of nitric acid and acetic acid.