SiP White Paper V9.0 The next Step in Assembly and Packaging: System Level Integration in the package (SiP) Our intent is that this paper will be a living document that is kept up to date as System in Package progresses and the technology evolves. We would like to ask the readers to send any suggestions and/or corrections to [email protected]. This will assist us in keeping the document up to date and accurate so that it can be a continuing reference to the state of the art in SiP and a guide to developments critical to meeting future market requirements. Page 1 SiP White Paper V9.0 Table of Contents 1. Executive Summary .................................................................................................. 5 Background .................................................................................................................. 6 Definition of SiP ........................................................................................................... 8 Level Structures ........................................................................................................... 8 SiP vs. SoC Comparison ............................................................................................. 11 Market Trends ............................................................................................................ 12 2. System Level Requirements for SiP ....................................................................... 13 2.1 General Requirements .................................................................................... 13 2.1.1 Consumer Markets drive Product Form Factors .................................. 13 3. Reliability Challenges ............................................................................................. 14 3.1.1 Complexity vs. Reliability ...................................................................... 15 3.1.2 Miniaturization vs. Reliability ............................................................... 15 3.1.3 Power vs. Reliability ............................................................................... 15 3.1.4 Yield vs. Reliability ................................................................................. 16 3.1.5 Materials Selection vs. Reliability ......................................................... 16 3.1.6 End Use Conditions vs. Reliability ........................................................ 16 3.2 Interconnect Reliability ....................................................................................... 17 3.3 Interconnect Reliability of PoP ............................................................................ 18 3.4 Interconnect Reliability of Stacked Die Packages .............................................. 21 3.5 Failure classification and mechanisms ............................................................... 22 4. Simulation Tool Requirements ............................................................................... 25 4.1 SiP Electrical Simulation Tools Requirements ................................................... 25 4.2 SiP Mechanical Simulation Tools Requirements ................................................ 26 4.3 Thermal Simulation Tools Requirements ......................................................... 27 4.4 Lifetime Models and Acceleration Factors .......................................................... 28 5. Requirements for Performance ............................................................................... 28 5.1. Electrical Performance Issues with SiP......................................................... 28 5.2 Electrical Performance - I/O Trends .................................................................... 29 6. Power Requirements ............................................................................................... 31 6.1 Electrical Current Density .................................................................................. 32 6.2 Voltage .................................................................................................................. 34 6.3 Power Integrity .................................................................................................... 35 6.3.1 Power Delivery ....................................................................................... 35 6.3.2 Electromagnetic Compatibility .............................................................. 38 7. Thermal Management ............................................................................................ 39 7. I. Hot spots ............................................................................................................. 41 7.2. Component temperature limits .......................................................................... 42 7.3. System thermal dissipation requirements ......................................................... 42 7.4 Thermal issues for Processors and Memory ....................................................... 43 8. Equipment and Assembly Issues ............................................................................ 44 8.1 Equipment Requirements and Challenges ......................................................... 45 8.2 Assembly requirements and challenges .............................................................. 46 8.2.1 Wire Bonding .......................................................................................... 47 8.2.2 Flip Chip ................................................................................................. 48 8.2.3 Molding ................................................................................................... 49 8.3. SiP Assembly Line Organization ........................................................................ 50 9. Challenges and Requirements for Materials and Processes ................................. 50 9.1 SiP Substrate and Assembly Processing ............................................................. 50 9.2 Alternate Substrate Materials ............................................................................. 51 9.3 SiP Assembly Challenges ..................................................................................... 53 9.4 Challenges of low k and ultra-low k dielectrics .................................................. 53 9.5 Die bonding for SiP .............................................................................................. 55 Page 2 SiP White Paper V9.0 9.6 Challenges requiring future Development .......................................................... 56 10. SiP for Specialized Functions ............................................................................... 56 10.1 CPU and Memory ............................................................................................... 56 10.2 High Power SiP .................................................................................................. 57 10.3 Optoelectronic Components in SiP .................................................................... 57 10.4 RF and Millimeter Wave Packaging.................................................................. 61 10.5 Medical and Bio Chip Packaging ....................................................................... 62 11. Operating Environment Specification .................................................................. 63 12. MEMS .................................................................................................................... 65 13. Chip-Package-System Co-design .......................................................................... 66 13.1. Introduction ....................................................................................................... 66 13.2. The Challenge ................................................................................................... 67 13.3. Cost and Time to Market .................................................................................. 67 13.4. Need for a Systematic Approach ...................................................................... 67 13.5 Design for Reliability: Impact on SiP ................................................................ 68 13.6. The Need for Co-Design Tool Development ..................................................... 69 13.7. Chip-Package-System Mechanical/Stress Modeling and Design Challenges . 69 13.8. Chip-Package-System Electrical Modeling and Design Challenges ............... 71 13.9. Chip-Package-System Thermal Modeling and Design Challenges ................. 73 13.10. Generic Chip-Package-System Co-Design Tool Development Requirements74 13.11. Proposed Chip-Package-System Co-design Methodologies and Tools ........... 75 13.12. A Future Vision of Chip-Package-System Co-Design .................................... 76 13.13. Stress/Mechanical Modeling and Design Co-Design Solutions ..................... 76 13.14. Thermal chip-package-system Co-design Solutions ...................................... 78 13.15. Electrical Chip-Package-System Co-design Solutions ................................... 81 13.16 RF Chip-Package-System Co-design Solutions .............................................. 83 13.17. Conclusion ....................................................................................................... 85 14. Application Specific Physical Architecture .......................................................... 85 14.1 Hand-held Applications ..................................................................................... 86 14.2 Low-cost Applications