External Memory Interface Handbook Volume 3: Reference Material Updated for Intel® Quartus® Prime Design Suite: 17.0 Subscribe EMI_RM | 2017.05.08 Send Feedback Latest document on the web: PDF | HTML Contents Contents 1. Functional Description—UniPHY.................................................................................... 13 1.1. I/O Pads............................................................................................................. 14 1.2. Reset and Clock Generation...................................................................................14 1.3. Dedicated Clock Networks.....................................................................................14 1.4. Address and Command Datapath........................................................................... 15 1.5. Write Datapath.................................................................................................... 16 1.5.1. Leveling Circuitry..................................................................................... 17 1.6. Read Datapath.................................................................................................... 18 1.7. Sequencer.......................................................................................................... 19 1.7.1. Nios II-Based Sequencer...........................................................................20 1.7.2. RTL-based Sequencer............................................................................... 25 1.8. Shadow Registers................................................................................................ 26 1.8.1. Shadow Registers Operation......................................................................27 1.9. UniPHY Interfaces................................................................................................ 28 1.9.1. The DLL and PLL Sharing Interface............................................................. 29 1.9.2. The OCT Sharing Interface........................................................................ 30 1.10. UniPHY Signals.................................................................................................. 32 1.11. PHY-to-Controller Interfaces................................................................................ 35 1.12. Using a Custom Controller...................................................................................39 1.13. AFI 3.0 Specification...........................................................................................40 1.13.1. Bus Width and AFI Ratio..........................................................................40 1.13.2. AFI Parameters...................................................................................... 41 1.13.3. AFI Signals............................................................................................42 1.14. Register Maps....................................................................................................46 1.14.1. UniPHY Register Map.............................................................................. 47 1.14.2. Controller Register Map...........................................................................49 1.15. Ping Pong PHY................................................................................................... 49 1.15.1. Ping Pong PHY Feature Description........................................................... 49 1.15.2. Ping Pong PHY Architecture......................................................................51 1.15.3. Ping Pong PHY Operation.........................................................................52 1.16. Efficiency Monitor and Protocol Checker................................................................ 52 1.16.1. Efficiency Monitor...................................................................................53 1.16.2. Protocol Checker.................................................................................... 53 1.16.3. Read Latency Counter.............................................................................53 1.16.4. Using the Efficiency Monitor and Protocol Checker.......................................53 1.16.5. Avalon CSR Slave and JTAG Memory Map.................................................. 54 1.17. UniPHY Calibration Stages................................................................................... 55 1.17.1. Calibration Overview...............................................................................55 1.17.2. Calibration Stages.................................................................................. 56 1.17.3. Memory Initialization.............................................................................. 57 1.17.4. Stage 1: Read Calibration Part One—DQS Enable Calibration and DQ/DQS Centering................................................................................... 57 1.17.5. Stage 2: Write Calibration Part One.......................................................... 62 1.17.6. Stage 3: Write Calibration Part Two—DQ/DQS Centering..............................63 1.17.7. Stage 4: Read Calibration Part Two—Read Latency Minimization................... 63 1.17.8. Calibration Signals..................................................................................64 1.17.9. Calibration Time.....................................................................................64 External Memory Interface Handbook Volume 3: Reference Material Send Feedback 2 Contents 1.18. Document Revision History..................................................................................64 2. Functional Description—Intel Stratix® 10 EMIF IP........................................................ 67 2.1. Stratix 10 Supported Memory Protocols.................................................................. 67 2.2. Stratix 10 EMIF IP Support for 3DS/TSV DDR4 Devices............................................. 68 2.3. Migrating to Stratix 10 from Previous Device Families............................................... 68 2.4. Stratix 10 EMIF Architecture: Introduction...............................................................68 2.4.1. Stratix 10 EMIF Architecture: I/O Subsystem...............................................69 2.4.2. Stratix 10 EMIF Architecture: I/O Column....................................................70 2.4.3. Stratix 10 EMIF Architecture: I/O SSM........................................................ 71 2.4.4. Stratix 10 EMIF Architecture: I/O Bank....................................................... 71 2.4.5. Stratix 10 EMIF Architecture: I/O Lane........................................................72 2.4.6. Stratix 10 EMIF Architecture: Input DQS Clock Tree......................................74 2.4.7. Stratix 10 EMIF Architecture: PHY Clock Tree............................................... 75 2.4.8. Stratix 10 EMIF Architecture: PLL Reference Clock Networks.......................... 75 2.4.9. Stratix 10 EMIF Architecture: Clock Phase Alignment.................................... 76 2.5. Hardware Resource Sharing Among Multiple Stratix 10 EMIFs.................................... 77 2.5.1. I/O SSM Sharing......................................................................................77 2.5.2. I/O Bank Sharing..................................................................................... 78 2.5.3. PLL Reference Clock Sharing......................................................................79 2.5.4. Core Clock Network Sharing...................................................................... 80 2.6. Stratix 10 EMIF IP Component...............................................................................81 2.6.1. Instantiating Your Stratix 10 EMIF IP in a Qsys Project.................................. 81 2.6.2. File Sets................................................................................................. 84 2.6.3. Customized readme.txt File....................................................................... 84 2.6.4. Clock Domains.........................................................................................85 2.6.5. ECC in Stratix 10 EMIF IP..........................................................................85 2.7. Examples of External Memory Interface Implementations for DDR4............................ 87 2.8. Stratix 10 EMIF Sequencer....................................................................................92 2.8.1. Stratix 10 EMIF DQS Tracking.................................................................... 93 2.9. Stratix 10 EMIF Calibration....................................................................................93 2.9.1. Stratix 10 Calibration Stages .................................................................... 94 2.9.2. Stratix 10 Calibration Stages Descriptions................................................... 94 2.9.3. Stratix 10 Calibration Algorithms................................................................95 2.9.4. Stratix 10 Calibration Flowchart................................................................. 98 2.10. Stratix 10 EMIF and SmartVID............................................................................. 99 2.11. Stratix 10 Hard Memory Controller Rate Conversion Feature.................................... 99 2.12. Differences Between User-Requested Reset in Stratix 10 versus Arria 10................. 100 2.12.1. Method for Initiating a User-requested Reset............................................101 2.13. Compiling