Reconstructing Pong on an FPGA Stephen A. Edwards Department of Computer Science, Columbia University h¶h«–þóì–Õó, December óþÕó Abstract I describe in detail the circuitry of the original ÕÉßó Pong video arcade game and how I reconstructed it on an £Z—a modern-day programmable logic device. In the original circuit, I discover some sloppy timing and a previously unidentied bug that subtly aected gameplay. I emulate the quasi-synchronous behavior of the original circuit by running a synchronous “simulation” circuit with a ó× clock and replacing each ip-op with a circuit that eectively simulates one. e result is an accurate reproduction that exhibits many idiosyncracies of the original. Õ Pong Circuit Descriptionó Õ.Õ e Main Clock...................................ó Õ.ó e Horizontal Counter...............................ó Õ.ì e Vertical Counter................................¢ Õ.¦ Horizontal and Vertical Sync............................¢ Õ.¢ e Net........................................ß Õ.ä e Paddles......................................ß Õ.ß e Score.......................................É Õ. Horizontal Ball Control...............................ÕÕ Õ.É Vertical Ball Control................................. Õ¢ Õ.Õþ Video Generation.................................. Õß Õ.ÕÕ Sound......................................... Õß Õ.Õó Game Control.................................... ÕÉ ó Reconstructing Pong on an FPGA óÕ ó.Õ Handling Quasi-Synchronous Circuits...................... óÕ ó.ó A Minimal Hardware Description Language................... óó ó.ì I/O on the Terasic ouó board............................ ó¢ ì Conclusions óä Õ Introduction is work started with a desire to play Pong, Atari’s ÕÉßó video arcade game that eectively launched the industry [ÕÕ]. While I could have sought out one of the few remaining machines, I chose instead to reconstruct it on an £Z, much as I had done for the Apple II computer [ß] and others have done for various other classic video arcade games []. Pong and other early games were implemented largely with discrete ±± chips, hence my choice of an £Z. By contrast, most later games were processor-based and have been successfully emulated in soware using an instruction-set simulator interacting with a high- level ad hoc simulator for the video hardware [É]. While modern processors are vastly faster than the roughly ß MHz clock frequency of Pong and many have written Pong-like programs in soware, my goal was precise (cycle-accurate) emulation. I ruled out doing so in soware because I expect it would be dicult to implement a soware circuit simulator able to consistently run this fast. However, while the Pong circuit is ostensibly synchronous, it is actually littered with ripple counters, §« latches built from discrete Zo gates, and ip-ops clocked from combinational logic, all of which are anathema to robust £Z designs. Below, I describe the circuit of the original Pong with a focus on its timing and analog components (§Õ), then describe my technique for reconstructing it on a modern-day, fully synchronous £Z (§ó). Õ Pong Circuit Description In addition to reading the schematics for Pong that can be found online (they appear to have been scanned from service manuals), Dan Boris [¦] presents an extensive description of the circuit; much of what I write here is derived from his work, especially his division of the circuit into sections. Arkush [Õ¢] also describes part of the circuitry in Pong, focusing closely on how counters are used to control the position of the ball. Õ.Õ e Main Clock FigureÕ shows the main clock generator: a Õ¦.ìÕ MHz crystal oscillator Õ driving a Zo gate driving a ip-ip that halves the frequency and generates a ¢þÛ duty-cycle square wave: the ß.Õ¢É MHz master clock. Õ¦.ìÕ MHz is a common crystal frequency in video circuits because it is four times the ±«h colorburst frequency of ìÕ¢/ MHz = ì.¢ßÉ¢¦¢ MHz. Pong, however, is black-and-white so another frequency could have been used. Õ.ó e Horizontal Counter e horizontal counter (Figureó), built from two ߦÉìs ( and É) and a ߦÕþß (ä), keeps track of the horizontal position of the video beam. e ߦÉì is a four-bit ripple counter built from four negative-edge-triggered ± ip-ops. Õe frequency is not labeled on the schematic, but multiple sources, including schematics of Pong clones, conrm this value. 14.318 MHz 100pF 330Ω 330Ω C9e 0.1µF C9d 11 10 9 8 7404 7404 1 3 12 1 J Q CLK E6d 11 12 F6a 13 7400 4 74107 2 1 K Q 13 1 Figure Õ: e main clock oscillator. is generates a ß.Õ¢É MHz square wave. Abstractly, the eight-input Zo ß detects the count ó¢ä + Õó + ä¦ + ¦ + ó = ¦¢¦ and causes the counter to reset, but the behavior is slightly more subtle, as shown in Figure¦. Because the ripple counters are triggered on the negative edge of the clock but the output of ß is buered by the positive-edge-triggered o ip-ip ußb, the count ¦¢¦ is only seen for half a clock period while the count þ is seen for one-and-a-half clock periods because the §u«u± signal only rises aer the next rising edge of the clock, eectively surpressing the count on the next falling edge of the clock. e period of §u«u± is thus ß.Õ¢É MHz~¦¢¢ = Õ¢.ßì¦ kHz, exactly the ±«h horizontal frequency. e horizontal counter is one of the most active parts of the circuit, yet Alcorn used slower, more problematic ripple counters instead of synchronous counters. Why he did this is not clear; one hypothesis is that it was a cost-saving measure: ߦÉìs were nearly half the price of ߦÕäÕs in ÕÉߢ [Õþ]. e use of ripple counters in the horizontal timing circuitry of these games appears to be characteristic of Alcorn. Bushnell’s earlier, more complex, and far less successful Computer Space (Nutting Associates, ÕÉßì) did use ߦÕäÕs [Õó]. Alcorn designed [ä] Atari’s ÕÉßì successor to Pong, Space Race [ÕÕ], and again used ߦÉìs [ì]. Atari’s ÕÉߦ Pin Pong, not designed by Alcorn, used synchronous counters (ÉìÕäs) [ó]. e presence of ripple counters makes the timing of this circuit worth discussing. In Figureó, I drew some of the internal structure of the counters to help explain the behavior of this circuit. e outputs Õ...ó¢ä do not change simultaneously: they ripple, which can be problematic for decoding particular columns. To decode ¦¢¦ as needed, fortunately, the delay is eectively modest because it is triggered by ó going high, which occurs only two ip-op delays aer the falling edge of the ß.Õ¢É MHz clock—all the other signals went high in a previous cycle and stay stable just before reaching a count of ¦¢¦. 3 2 3 2 1 7493 F8 7493 F9 8 5 J Q 14 14 CLK 9 F6b 11 74107 6 K Q 256H 12 1 9 8 11 12 1 9 8 11 10 1 1 11 12 5 10 F7 812 9 6 D Q HRESET 7430 11 E7b 2 7474 8 3 Q HRESET 1H 2H 8H 32H 128H 4H 16H 64H 256H 4 13 Figure ó: e horizontal counter: is counts þ, Õ, ..., ¦¢¦, generating a Õ¢.ßì¦ kHz horizontal frequency. 3 2 3 2 1 R02 R01 R02 R01 8 5 14 14 J Q HRESET CKA E8 CKA E9 9 D9b 1 1 CKB 7493 CKB 7493 11 74107 6 QA QB QC QD QA QB QC QD K Q 256V 12 9 8 11 12 9 8 11 10 9 4 10 D8c 82 5 D Q VRESET 11 7410 3 E7a 7474 6 Q VRESET 1 1 1V 2V 64V 128V 256V 4V 8V 16V 32V Figure ì: e vertical counter: is counts þ, Õ, ..., óäÕ CLK 7M 1H-256H 451 452 453 454 0 2 3 HRESET HBLANK 1V-256V 261 0 VRESET 1V-256V 0 1 VRESET 1V-256V 1 2 VRESET Figure ¦: Behavior of the horizontal and vertical counters at the end of a horizontal line Õ.ì e Vertical Counter e vertical counter (Figureì) is similar to the horizontal counter, but is clocked once per eld by the §u«u± signal generated by the horizontal counter and resets on a count of Õ + ¦ + ó¢ä = óäÕ. is gives a vertical refresh frequency of Õ¢.ßì¦ kHz~óäó = äþ.þ¢ Hz, which is certainly close enough to äþ Hz for most monitors. A strictly compliant (interlaced) ±«h signal actually has ¢ó¢~ó = óäó.¢ horizontal line periods per eld. Again the ߦÉìs are negative-edge triggered, so the vertical count changes when §u«u± falls and is reset when §u«u± rises—see Figure¦. Õ.¦ Horizontal and Vertical Sync Figure¢ shows the circuits for generating horizontal and vertical blanking and synchronization signals. ese are two §« latches built from discrete gates with some extra gating logic. Part of the timing of the horizontal blanking latch is problematic. e §u«u± signal is not a problem because it comes directly from a ip-op triggered by the clock (ußb, see Figureó, so fZ falls quickly aer the rising edge of the clock. However, for fZ to rise, ä¦ must be high and Zo ¢b looks for the rising edge of Õä (a count of ä¦ + Õä = þ). is is initiated by a falling edge on the ß MHz clock and occurs aer passing through ve ip-op stages (all of the ripple counter and the rst stage of É). Below is an accounting of delays based on numbers from ±’s ÕÉ data book [Õ¦]. 3 16H 4 G5b 64 H5b 6 5 7410 5 HBLANK 64H 7400 9 H5c 8 10 HBLANK HRESET 7400 12 H5d 11 13 HSYNC 32H 7400 8 VRESET F5c 10 9 7402 VBLANK 11 F5d 13 12 VBLANK 16V 7402 1 2 G5a 12 4V VSYNC 1 13 7410 8V H5a 3 2 7400 Figure ¢: Horizontal and Vertical Blanking and Sync CLK 7M 1H-256H 77 78 79 80 81 82 HBLANK Figure ä: Behavior of fZ near the start of the line.