The Design and Implementation of an Asynchronous Microprocessor A THESIS SUBMITTED TO THE UNIVERSITY OF MANCHESTER FOR THE DEGREE OF DOCTOR OF PHILOSOPHY IN THE FACULTY OF SCIENCE By Nigel Charles Paver Department of Computer Science 1994 Table of Contents Chapter 1 : Introduction .......................................................... 17 1.1 Motivation ....................................................................................... 17 1.1.1 Global synchronization .......................................................... 17 1.1.2 Performance ........................................................................... 18 1.1.3 Power consumption ............................................................... 18 1.2 Basic concepts ................................................................................. 19 1.2.1 Timing model ........................................................................ 19 1.2.2 Mode ...................................................................................... 19 1.2.3 Asynchronous signalling conventions ................................... 20 1.3 Objectives and thesis structure ........................................................ 22 1.3.1 Structure of the thesis ............................................................ 22 1.3.2 Author’s contribution ............................................................ 22 Chapter 2 : Related work ....................................................... 25 2.1 Automatic synthesis tools ................................................................ 25 2.1.1 CSP based compilation .......................................................... 25 2.1.2 Signal transition graphs ......................................................... 26 2.1.3 State machines ....................................................................... 27 2.2 Other related work ........................................................................... 27 2.3 Summary .......................................................................................... 28 2.3.1 Micropipelines ....................................................................... 28 2.3.2 AMULET group Micropipelines ........................................... 28 Chapter 3 : Micropipelines ................................................... 29 3.1 Basic concepts ................................................................................. 29 3.1.1 Event control modules ........................................................... 30 3.1.2 Metastability .......................................................................... 31 3.1.3 Event-controlled storage element .......................................... 32 3.2 Micropipelines ................................................................................. 33 3.2.1 A Micropipeline FIFO ........................................................... 33 3.2.2 Micropipelines with processing ............................................. 34 3.3 Event control module structures ...................................................... 34 3.3.1 Exclusive OR gate ................................................................. 35 3.3.2 Muller C-Gate ........................................................................ 36 3.3.3 Transparent latch ................................................................... 37 2 3.3.4 SELECT block ....................................................................... 37 3.3.5 Decision-Wait element .......................................................... 38 3.3.6 CALL block ........................................................................... 39 3.3.7 TOGGLE ............................................................................... 39 3.3.8 ARBITER .............................................................................. 41 3.3.9 Capture-Pass latch ................................................................. 43 3.3.10 Cell layout ........................................................................... 44 3.3.11 Implementation costs ........................................................... 44 3.4 Micropipeline implementation ........................................................ 46 3.4.1 The T-Latch Micropipeline ................................................... 47 3.4.2 The Capture-Pass Micropipeline ........................................... 49 3.4.3 Capture-Pass versus transparent latch area considerations ... 49 3.4.4 Micropipeline stage performance .......................................... 51 3.4.5 Power considerations ............................................................. 53 3.4.6 Choosing an implementation ................................................. 54 Chapter 4 : The asynchronous ARM ............................ 57 4.0.1 The ARM processor .............................................................. 57 4.0.2 Implementation challenges .................................................... 57 4.0.3 Differences from the ARM6 .................................................. 58 4.0.4 Processor interface ................................................................. 58 4.1 Processor organization ..................................................................... 60 4.1.1 Address interface ................................................................... 60 4.1.2 The register bank ................................................................... 60 4.1.3 The execution unit ................................................................. 60 4.1.4 The data interface .................................................................. 62 4.2 Pipeline organization and control ................................................... 62 4.2.1 Dynamic pipeline structure .................................................... 62 4.3 Instruction mapping ......................................................................... 64 4.3.1 Data operation ....................................................................... 65 4.3.2 Branch operation ................................................................... 66 4.3.3 Multiply operation ................................................................. 67 4.3.4 Load data operation ............................................................... 67 4.3.5 Store data operation ............................................................... 70 4.3.6 Block transfer operation ........................................................ 70 4.3.7 Exception entry operation ...................................................... 74 4.4 Instruction flow control ................................................................... 76 4.4.1 The ARM PC model and the PC pipeline ............................. 76 3 4.4.2 Condition code evaluation ..................................................... 76 4.4.3 Branch operations .................................................................. 77 4.5 Exception handling .......................................................................... 79 4.5.1 Hardware interrupts ............................................................... 79 4.5.2 Data abort overview .............................................................. 81 4.5.3 Data abort signalling .............................................................. 82 Chapter 5 : The register bank ............................................. 85 5.1 Register bank operation ................................................................... 85 5.1.1 Internal register structure ....................................................... 86 5.1.2 Register bank hazards ............................................................ 86 5.2 Write address storage ....................................................................... 87 5.2.1 An asynchronous register lock FIFO ..................................... 88 5.2.2 FIFO examination .................................................................. 89 5.2.3 Stalling reads ......................................................................... 90 5.3 Asynchronous register bank design ................................................. 90 5.3.1 Read and lock operations ....................................................... 90 5.3.2 Write operations .................................................................... 92 5.4 Additional features .......................................................................... 93 5.4.1 Dual lock FIFO ...................................................................... 93 5.5 Implementation ................................................................................ 94 5.6 Future enhancements - register bypassing ....................................... 96 5.6.1 Register through-passing ....................................................... 96 5.6.2 Last result re-use .................................................................... 97 Chapter 6 : Memory interface ............................................ 99 6.1 Address interface ............................................................................. 99 6.1.1 Load/Store multiple operation ............................................... 101 6.1.2 Changing the PC value .......................................................... 101 6.1.3 PC loop deadlock ................................................................... 102 6.1.4 PC pipeline ............................................................................ 103 6.1.5 Instruction overflow deadlock ............................................... 103 6.1.6 PCpipe implementation ........................................................