Commissioning of Protective Relay Systems Karl Zimmerman Schweitzer Engineering Laboratories, Inc. Presented at the 61st Annual Conference for Protective Relay Engineers College Station, Texas April 1–3, 2008 Previous revised edition released October 2007 Originally presented at the 34th Annual Western Protective Relay Conference, October 2007 1 Commissioning of Protective Relay Systems Karl Zimmerman, Schweitzer Engineering Laboratories, Inc. Abstract—Performing tests on individual relays is a common A. Tools and Methods for Commissioning Protective Relaying practice for relay engineers and technicians. Most utilities have a Systems wide variety of test plans and practices. However, properly com- missioning an entire protection system, not just the individual Some tools and methods that aid in the commissioning of relays, presents a challenge. protective relaying systems are listed here: This paper suggests a process for performing consistent and • I/O contact testing thorough commissioning tests through many sources: breaking • Functional element testing out relay logic into schematic drawings; using SER, metering, • State simulation testing and event reports from relays; simulating performance using end-to-end testing and lab simulations; and utilizing other tools, • SER, metering, and event report data including synchrophasor measurements. We examine and sug- • End-to-end tests using satellite-synchronized test sets gest approaches for commissioning several applications: distribu- • Synchrophasor data tion bus protection, short line protection using communications- • Logic diagrams that break out programmable logic aided tripping, main-tie-main scheme, line and transformer • Commissioning in the field differential protection. Finally, we propose that, while 100% commissioning certainty may not be possible, we can approach • Lab simulations 100% by integrating event report analysis to validate our com- • Use of system event reports to validate relay missioning strategy. performance as part of the commissioning strategy I. INTRODUCTION B. Developing a Plan Protective relays now perform many functions besides Testing requirements for every system are likely to be protection. The advantages that modern microprocessor-based different based on the system configuration and protection relays provide over traditional relays are well documented. scheme applied. Develop a test plan that captures all the nec- These advantages include fault location, event reports, and essary steps to ensure that a system is tested with reasonable programmable logic that allow many functions to be included certainty. in one device, thus saving hardware and wiring costs. One Appendix A is a checklist developed for transmission line important complication of the technology shift is the increas- protection schemes and serves as a template for a customized ing portion of the protection system design that resides in and complete commissioning testing strategy. algorithms and logic in relays. Meanwhile, testing and commissioning practices largely III. COMMISSIONING EXAMPLES still focus on individual relays, not the protective relaying A. Fast Bus Protection on a Distribution Bus Using a system. How can we be certain that we are fully testing and Protection Logic Processor commissioning relay systems? Have we improved simplicity Fig. 1 shows a one-line diagram of a distribution bus pro- and reliability or just shifted the complexity? tection scheme using a fast bus trip scheme. II. CERTAINTY IN COMMISSIONING WITH NEW TECHNOLOGIES Few would disagree that implementing new technologies B6 85/69 with microprocessor-based relays has improved power system Protection Logic protection. This includes improved reliability by finding root 67 Processor cause of system faults, reduced cost of hardware and wiring, fault location, and many other advantages. 67 67 Traditional designs, typically electromechanical, have more devices and greatly increased wiring requirements. However, B3 B2 one advantage of single-purpose devices is that all of the functionality, for the most part, can be represented by a single elementary drawing. A technician can have a blueprint of the Fig. 1. Fast Bust Trip One-Line Diagram design and systematically highlight each device and Most of the logic for the protection of this scheme is devel- interconnection until the entire system is tested. oped in the settings of a protection logic processor (85/69 Certainty in commissioning protective relaying systems is, device). Thus, to successfully commission this scheme, we perhaps, the most difficult part of implementing new technolo- need to verify the performance of the following: gies. However, there are many tools and approaches we can • Directional overcurrent elements (67) use to improve and simplify this process. • Performance of the communications path 2 • CT and VT connections and polarities of the inputs to 5. Verify Transient Reversal Block logic by applying Test 1, the 67 devices then Test 4 in short intervals, e.g., apply Test 1 for 2 • Fast bus trip and block logic settings in relays and cycles, then Test 4 for 4 cycles, etc. (no TRIP). protection logic processor 6. Verify Disable Fast Bus Trip logic by applying loss of • Breaker trip/dc control circuit potential (LOP) and relay out of service conditions, then The directional overcurrent elements can be tested and vali- apply Test 4 (no TRIP). dated by applying test values from system faults (e.g., internal By performing a thorough lab simulation of the complete bus fault, external line faults). logic, we can then install and commission this system. In the CT and VT polarities, phasing, and ratios are usually field, we check the CTs and VTs, verify the integrity of the checked through manual field measurements at commission- communications path, and perform breaker trip tests to ing. One improvement is to use synchrophasor data from the validate the dc control circuit. relays, if available [1]. Phasor measurements take a precise B. Short Line Protection Using Directional Overcurrent snapshot of the currents and voltages at the same instant in Protection in Blocking and Permissive Pilot Tripping Schemes time. Commissioning the communications path and logic settings As shown in Fig. 3, a series of underground distribution is more complex and requires that the logic be broken out into lines (Loops 1, 2, 3, and 4) are protected by directional over- logic diagrams, like the one shown in Fig. 2. current protection in a pilot protection scheme. Essentially, Ideally, we would like to test the scheme all the way this system, even though it is a medium-voltage (15 kV) through. The best environment for this is a lab simulation with system, is protected like a transmission system [2]. all three relays and the protection logic processor connected Each line section uses a permissive overreaching transfer with complete ac voltage and current and the entire communi- trip (POTT) scheme and a directional comparison blocking cations scheme connected. (DCB) scheme. The permissive, block, and direct transfer trip For example, individually test directional overcurrent ele- signals are transmitted and received between the relays ments (67) for Breakers 2, 3, and 6. Then apply fault simula- through an optical fiber network using relay-to-relay tions for each scenario to verify the internal and external fault communications. Two separate fiber paths (A and B) are used. logic (expected results are shown in parentheses): To successfully commission these schemes, we need to verify the performance of the following: 1. Breakers 3, 6 internal, Breaker 2 external (no TRIP). • Directional overcurrent elements (67) 2. Breakers 2, 6 internal, Breaker 3 external (no TRIP). • Communications paths 3. Breakers 2, 3 internal, Breaker 6 external (no TRIP). • POTT and DCB tripping schemes 4. Breakers 2, 3, 6 internal (TRIP within 25 ms). • Primary voltage and current magnitude, polarity, and phasing LOP * ! Relay OOS Breaker 52A * Relay OOS Breaker 6 6 Internal Fault Channel 6 OK Fault Towards Bus Breaker 3 Fault Internal Fault 25 Fast Bus Towards Bus ms 32 Trip Breaker 6 ms External Fault Fault Away External 16 Transient ms From Bus Fault 160 Reversal Block ms Block Logic Breaker 3 External Fault LOP Breaker 2 Disable Relay Out Fast Bus of Service Trip 52A Channel 2 OK LOP * ! Relay OOS Breaker 52A* Relay OOS 3 Channel 3 OK Fig. 2. Fast Bus Trip Logic 3 + P P 67P2 67G2 52B KEY Radial 1 P Transmit * Permissive A (to remote) North Received Radial 2 Substation KEY Permissive A * (from remote) V V Comm A OK V V V Loop 4 Transmit TRIP DTT A V (to remote) * V V Automated Switch 3 Miles V * – V V P Automated Pad-Mounted V Switchgear Fig. 5. Control Circuit Representation of POTT Logic V Loop 3 Relayed Fault-Interrupter V V V 2) DCB Scheme Switchgear V V V Fig. 6 and Fig. 7 show the basic DCB scheme one-line * Indicates Normally Open diagram and control circuit representation, respectively. The V V Tie Point * * DCB scheme is used in conjunction with the POTT scheme to V V Loop 2 ensure tripping occurs with no settings changes if the system V V * is run as an open-loop (radial) system. V V V V V Forward directional overcurrent elements (67P2T, 67G2T) V V Loop 1 * V trip provided no block is received from the remote terminal. Reverse elements (67P3, 67G3) assert the transmit block South signal. There is a short 3-cycle delay on the tripping for DCB Substation to allow time for the block to be received. Fig. 3. System One-Line Diagram of Loop Distribution System Protected Zone 1) POTT Scheme Fig. 4 shows a POTT scheme one-line diagram. As we can 1 2 67P2T, 67G2T see, phase and ground directional overcurrent elements (67P2, 67G2) declare faults in the forward direction. 67P3, 67G3 Protected Zone Fig. 6. Basic DCB Scheme Protection 1 2 + 67P2, 67G2 67P2T 67G2T 67P3 67G3 TDPU TDPU 67P2, 67G2 Fig. 4. Basic POTT Scheme Protection Transmit Block A The logic for tripping, as well as transmitting and receiving (to remote) permissive trip signals, resides within the relay. Fig. 5 shows a Received Block A NC (from remote) control circuit representation of the logic.