CHALLENGES AND SOLUTIONS FOR LARGE-SCALE INTEGRATION OF EMERGING TECHNOLOGIES A Dissertation IN Electrical and Computer Engineering and Physics Presented to the Faculty of the University of Missouri–Kansas City in partial fulfillment of the requirements for the degree DOCTOR OF PHILOSOPHY by Md Arif Iqbal B.Sc., Khulna University of Engineering and Technology, Khulna, Bangladesh, 2010 Kansas City, Missouri 2021 © 2021 MD ARIF IQBAL ALL RIGHTS RESERVED CHALLENGES AND SOLUTIONS FOR LARGE-SCALE INTEGRATION OF EMERGING TECHNOLOGIES Md Arif Iqbal, Candidate for the Doctor of Philosophy Degree University of Missouri–Kansas City, 2021 ABSTRACT The semiconductor revolution so far has been primarily driven by the ability to shrink devices and interconnects proportionally (Moore's law) while achieving incremental benefits. In sub-10nm nodes, device scaling reaches its fundamental limits, and the interconnect bottleneck is dominating power and performance. As the traditional way of CMOS scaling comes to an end, it is essential to find an alternative to continue this progress. However, an alternative technology for general-purpose computing remains elusive; currently pursued research directions face adoption challenges in all aspects from materials, devices to architecture, thermal management, integration, and manufacturing. Crosstalk Computing, a novel emerging computing technique, addresses some of the challenges and proposes a new paradigm for circuit design, scaling, and security. However, like other emerging technologies, Crosstalk Computing also faces challenges like designing large-scale circuits using existing CAD tools, scalability, evaluation and benchmarking of large-scale designs, experimentation through commercial foundry processes to compete/co- exist with CMOS for digital logic implementations. This dissertation addresses these issues by providing a methodology for circuit synthesis customizing the existing EDA tool flow, evaluating and benchmarking against state- of-the-art CMOS for large-scale circuits designed at 7nm from MCNC benchmark suits. This iii research also presents a study on Crosstalk technology's scalability aspects and shows how the circuits' properties evolve from 180nm to 7nm technology nodes. Some significant results are for primitive Crosstalk gate, designed in 180nm, 65nm, 32nm, and 7nm technology nodes, the average reduction in power is 42.5%, and an average improvement in performance is 34.5% comparing to CMOS for all mentioned nodes. For benchmarking large-scale circuits designed at 7nm, there are 48%, 57%, and 10% improvements against CMOS designs in terms of density, power, and performance, respectively. An experimental demonstration of a proof- of-concept prototype chip for Crosstalk Computing at TSMC 65nm technology is also presented in this dissertation, showing the Crosstalk gates can be realized using the existing manufacturing process. Additionally, the dissertation also provides a fine-grained thermal management approach for emerging technologies like transistor-level 3-D integration (Monolithic 3-D, Skybridge, SN3D), which holds the most promise beyond 2-D CMOS technology. However, such 3-D architectures within small form factors increase hotspots and demand careful consideration of thermal management at all integration levels. This research proposes a new direction for fine-grained thermal management approach for transistor-level 3-D integrated circuits through the insertion of architected heat extraction features that can be part of circuit design, and an integrated methodology for thermal evaluation of 3-D circuits combining different simulation outcomes at advanced nodes, which can be integrated to traditional CAD flow. The results show that the proposed heat extraction features effectively reduce the temperature from a heated location. Thus, the dissertation provides a new perspective to overcome the challenges faced by emerging technologies where the device, circuit, connectivity, heat management, and manufacturing are addressed in an integrated manner. iv APPROVAL PAGE The faculty listed below, appointed by the Dean of the School of Graduate Studies, have examined a thesis titled “Challenges and Solutions For Large-Scale Integration of Emerging Technologies” presented by Md Arif Iqbal, candidate for the Doctor Of Philosophy degree, and certify that in their opinion it is worthy of acceptance. Supervisory Committee Mostafizur Rahman, Ph.D., Committee Chair Department of Computer Science & Electrical Engineering Paul Rulis, Ph.D. Department of Physics & Astronomy Masud Chowdhury, Ph.D. Department of Computer Science & Electrical Engineering Ghulam Chaudhry, Ph.D. Department of Computer Science & Electrical Engineering Cory Beard, Ph.D. Department of Computer Science & Electrical Engineering v CONTENTS ABSTRACT ...................................................................................................................... iii ILLUSTRATIONS .......................................................................................................... viii TABLES ............................................................................................................................. xi ACRONYMS .................................................................................................................... xii ACKNOWLEDGEMENTS ............................................................................................. xiii Chapter 1 INTRODUCTION AND MOTIVATION .......................................................... 1 Chapter 2 CROSSTALK COMPUTING OVERVIEW ...................................................... 6 2.1 Crosstalk Primitive Gates ........................................................................................ 7 2.2 Crosstalk Circuits Based on Coupling Weight ........................................................ 9 Chapter 3 LOGIC SIMPLIFICATION APPROACH FOR CROSSTALK CIRCUIT DESIGN ....................................................................................................................... 12 3.1 Formal Synthesis Methods .................................................................................... 12 3.2 Majority Network-Based Synthesis ....................................................................... 13 3.3 SIS Tool ................................................................................................................. 13 3.4 Crosstalk Computing Logic Simplification ........................................................... 14 3.4.1 Overview of The Proposed Logic Simplification Methodology .............. 15 3.5 Section Summary ................................................................................................... 23 Chapter 4 CROSSTALK COMPUTING SCALABILITY STUDY: FROM 180NM TO 7NM ............................................................................................................................. 24 4.1 Scalability Aspects of Crosstalk Circuits .............................................................. 25 4.2 Section Summary ................................................................................................... 27 Chapter 5 DESIGNING LARGE-SCALE CIRCUITS IN CROSSTALK at 7nm ............ 28 5.1 Crosstalk Basic Gates Design at 7nm under Process Variation ............................ 29 5.2 Designing Under Variation at 7nm ........................................................................ 31 5.3 Designing Large-Scale Circuits at 7nm ................................................................. 33 5.4 Section Summary ................................................................................................... 36 Chapter 6 COMPARISON AND BENCHMARKING ..................................................... 38 vi 6.1 Comparison of Density Benefit Using Different Boolean Network ...................... 38 6.2 Benchmark of Different Large Circuits ................................................................. 39 6.3 Section Summary ................................................................................................... 40 Chapter 7 EXPERIMENTAL DEMONSTRATION OF CROSSTALK COMPUTING . 42 7.1 Technology Description ......................................................................................... 42 7.2 Post Fabrication Results ........................................................................................ 44 7.3 Section Summary ................................................................................................... 45 Chapter 8 THERMAL MANAGEMENT CHALLENGES AND MITIGATION TECHNIQUES FOR TRANSISTOR-LEVEL 3-D INTEGRATION ........................ 46 8.1 Overview of Transistor-Level 3-D Integration Approaches .................................. 48 8.1.1 Skybridge [67].......................................................................................... 48 8.1.2 Stacked Horizontal Nanowire Based 3-D CMOS (SN3D) [68] .............. 49 8.1.3 Monolithic 3-D CMOS [66] ..................................................................... 49 8.2 Thermal Management by Architecting Specialized Physical Fabric Features ...... 50 8.3 Finite Element Modeling and Simulation Approach ............................................. 52 8.3.1 Methodology ............................................................................................ 53 8.3.2 Principles for FEM Thermal Conduction Modeling ................................ 54 8.3.3 Thermal Contact Resistance Modeling .................................................... 55 8.3.4 Thermal Modeling