System-on-Chip Design with Arm® Cortex®-M Processors Reference Book JOSEPH YIU System-on-Chip Design with Arm® Cortex®-M Processors System-on-Chip Design with Arm® Cortex®-M Processors Reference Book JOSEPH YIU Arm Education Media is an imprint of Arm Limited, 110 Fulbourn Road, Cambridge, CBI 9NJ, UK Copyright © 2019 Arm Limited (or its affiliates). All rights reserved. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying, recording or any other information storage and retrieval system, without permission in writing from the publisher, except under the following conditions: Permissions You may download this book in PDF format from the Arm.com website for personal, non- commercial use only. You may reprint or republish portions of the text for non-commercial, educational or research purposes but only if there is an attribution to Arm Education. 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ISBN: 978-1-911531-19-7 Version: 1.0.3 – pdf For information on all Arm Education Media publications, visit our website at https://www.arm.com/resources/education/books To report errors or send feedback please email [email protected] To our families Contents Foreword xiv Preface xviii Example Codes and Projects / Disclaimer / A note about the scope of this book xix About the Author xx Acknowledgments xxi 1. Introduction to Arm Cortex-M 1.1 Why learn Cortex-M system design? 2 1.1.1 Starting Cortex-M system design is easy 2 1.1.2 Cortex-M processor systems on FPGA 3 1.1.3 Security by design is made easier with Arm architecture 4 1.2 Understanding different types of Arm processors 4 1.3 Cortex-M deliverables 7 1.3.1 Licensing through Arm Flexible Access and Arm DesignStart 7 1.3.2 Obfuscated Verilog – DesignStart Eval 8 1.3.3 Verilog RTL sources – DesignStart Pro 9 1.3.4 FPGA Packages – DesignStart FPGA 9 1.3.5 Documentation 9 2. Introduction to system design with Cortex-M processors 2.1 Overview of Cortex-M Processors 12 2.2 What memories are needed? 13 2.2.1 Overview of memories 13 2.2.2 Memory declarations in FPGA design tools 14 2.2.3 Memory handling in ASIC designs 16 2.2.4 Memory endianness 17 2.3 Defining the peripherals 17 2.4 Memory map definition 18 2.5 Bus and memory system design 20 2.6 TCM integration 21 2.7 Cache integration 21 2.8 Defining the processor’s configuration options 22 2.9 Interrupt signals and related areas 22 vii Contents 2.10 Event interface 24 2.11 Clock generation 25 2.12 Reset generation 27 2.13 SysTick 29 2.14 Debug integration 30 2.15 Power management features 31 2.16 Top-level pin assignment and pin multiplexing 31 2.17 Miscellaneous signals 32 2.18 Sign off requirements 32 3. AMBA, AHB, and APB 3.1 What is AMBA? 36 3.1.1 Introduction to Advanced Microcontroller Bus Architecture 36 3.1.2 History of AMBA 36 3.1.3 Various versions of AMBA specification 37 3.2 Overview of AHB 38 3.2.1 Various versions of AHB 38 3.2.2 AHB signals 38 3.2.3 Basic operations 40 3.2.4 Minimal AHB systems 42 3.2.5 Handling of multiple bus masters 43 3.3 More details on the AHB protocol 45 3.3.1 Address phase signals 45 3.3.2 Data phase signals 51 3.3.3 Legacy arbiter handshake signals 55 3.4 Exclusive access operations 57 3.4.1 Introduction to exclusive accesses 57 3.4.2 AHB5 exclusive access support 60 3.4.3 Mapping of Cortex-M3/M4/M7 exclusive access signals to AHB5 61 3.5 AHB5 TrustZone support 62 3.6 Overview of APB 63 3.6.1 Introduction to the APB bus system 63 3.6.2 APB signals and connection 64 viii Contents 3.6.3 Additional signals in APB protocol v2.0 68 3.6.4 Data values on APB 69 3.6.5 Mixing different versions of APB components 69 4. Building simple bus systems for Cortex-M processors 4.1 Introduction to the basics of bus design 72 4.2 Building a simple Cortex-M0 system 73 4.3 Building a simple Cortex-M0+ system 74 4.4 Building a simple Cortex-M1 system 76 4.5 Building a simple Cortex-M3/Cortex-M4 system 78 4.6 Handling multiple bus masters 84 4.7 Exclusive access support 86 4.8 Address remap 88 4.9 AHB- based memory connection versus TCM 89 4.10 Handling of embedded flash memories 91 4.10.1 IP requirements 91 4.10.2 Flash programming 91 4.10.3 Bringing up a new device without a valid program image 92 5. Debug integration with Cortex-M processor systems 5.1 Overview of debug and trace features 96 5.2 CoreSight Debug Architecture 98 5.2.1 Introduction to Arm CoreSight 98 5.2.2 Debug connection protocols 99 5.2.3 Debug connection concept - Debug Access Port (DAP) 100 5.2.4 Various arrangements of debug interface structure 101 5.2.5 Trace connection concept 102 5.2.6 Timestamp 104 5.2.7 Debug components discovery (ROM table and component IDs) 104 5.2.8 Debug authentication 106 5.2.9 Debug power request 107 5.2.10 Debug reset request 108 5.2.11 Cross Trigger Interface 108 ix Contents 5.3 Debug integration 109 5.3.1 JTAG / Serial Wire Debug connections 109 5.3.2 Trace port connections 110 5.3.3 Clocks for the debug and trace system 111 5.3.4 Multi-drop serial wire support 113 5.3.5 Debug authentication 114 5.4 Other related topics 116 5.3.1 Other signal connections 116 5.3.2 Daisy chain of JTAG connection 116 6. Low-power support 6.1 Overview of low-power Cortex-M features 120 6.2 Low-power design basics 121 6.3 Cortex-M low-power interfaces 123 6.3.1 Sleep status and GATEHCLK output 123 6.3.2 Q-channel low-power interface (Cortex-M23, Cortex-M33, Cortex-M35P) 124 6.3.3 Sleep hold interface 126 6.3.4 Wakeup Interrupt Controller (WIC) 128 6.3.5 SRPG’s impact on software 132 6.3.6 Software power-saving approach 132 6.4 Cortex-M processor characteristics that enable low-power designs 133 6.4.1 High code density 133 6.4.2 Short pipeline 133 6.4.3 Instruction fetch optimizations 134 6.5 System-level design considerations 135 6.5.1 Low-power designs overview 135 6.5.2 Clock sources 135 6.5.3 Low-power memories 135 6.5.4 Caches 135 6.5.5 Low-power analog components 136 6.5.6 Maximizing clock gating opportunities 136 6.5.7 Sleep mode that completely powers down the processor 137 x Contents 7. Design of bus infrastructure components 7.1 Overview of a simple AMBA system design 142 7.2 Typical AHB slave design rules 144 7.3 Typical AHB infrastructure components 146 7.3.1 AHB decoders 146 7.3.2 Default slave 147 7.3.3 AHB Slave multiplexer 149 7.3.4 ROM and RAM with AHB interface 151 7.3.5 AHB to APB Bridge 159 7.4 Bridging from Cortex-M3/Cortex-M4 AHB Lite to AHB5 168 8. Design of simple peripherals 8.1 Common practices for peripheral designs 172 8.2 Designing Simple APB Peripherals 173 8.2.1 General Purpose Input Output (GPIO) interface 180 8.2.2 Simple APB Timer 186 8.2.3 Simple UART 190 8.3 ID registers 199 8.4 Other peripheral design considerations 200 8.4.1 Security of system control functions 200 8.4.2 Processor’s halting 200 8.4.3 Handling of 64-bit data 200 9. Putting the system together 9.1 Creating a simple microcontroller-like system 204 9.2 Design partitioning 205 9.3 What is inside a simulation environment? 206 9.4 Prepare the minimal software support for simulation 207 9.4.1 Overview of example code based on CMSIS-CORE 207 9.4.2 Device header file for example MCU (cm3_mcu.h) 208 9.4.3 Device start-up file for example MCU (startup_cm3_mcu.s) 211 9.4.4 UART utilities 212 9.4.5 System initialization function 213 xi Contents 9.4.6 Retargeting 214 9.4.7 Other software support package considerations 215 9.5 System-level simulation 216 9.5.1 Compiling hello world 216 9.5.2 Using Modelsim/QuestaSim to compile and simulate the design 217 9.6 Advanced processor systems and Corstone Foundation IP 220 9.7 Verification 221 9.8 ASIC implementation flow 223 9.9 Design for Testing/Testability (DFT) 224 10.