Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook Subscribe A10-HANDBOOK | 2020.06.30 Send Feedback Latest document on the web: PDF | HTML Contents Contents 1. Logic Array Blocks and Adaptive Logic Modules in Intel® Arria® 10 Devices................... 7 1.1. LAB..................................................................................................................... 7 1.1.1. MLAB....................................................................................................... 8 1.1.2. Local and Direct Link Interconnects ............................................................. 9 1.1.3. Shared Arithmetic Chain and Carry Chain Interconnects ............................... 10 1.1.4. LAB Control Signals..................................................................................11 1.1.5. ALM Resources ....................................................................................... 12 1.1.6. ALM Output ............................................................................................13 1.2. ALM Operating Modes ..........................................................................................14 1.2.1. Normal Mode ..........................................................................................14 1.2.2. Extended LUT Mode..................................................................................17 1.2.3. Arithmetic Mode ..................................................................................... 18 1.2.4. Shared Arithmetic Mode ...........................................................................20 1.3. LAB Power Management Techniques ...................................................................... 21 1.4. Logic Array Blocks and Adaptive Logic Modules in Intel Arria 10 Devices Revision History............................................................................................................ 21 2. Embedded Memory Blocks in Intel Arria 10 Devices......................................................22 2.1. Types of Embedded Memory..................................................................................22 2.1.1. Embedded Memory Capacity in Intel Arria 10 Devices................................... 23 2.2. Embedded Memory Design Guidelines for Intel Arria 10 Devices................................. 23 2.2.1. Consider the Memory Block Selection..........................................................23 2.2.2. Guideline: Implement External Conflict Resolution........................................ 24 2.2.3. Guideline: Customize Read-During-Write Behavior........................................24 2.2.4. Guideline: Consider Power-Up State and Memory Initialization....................... 27 2.2.5. Guideline: Control Clocking to Reduce Power Consumption............................ 28 2.3. Embedded Memory Features................................................................................. 28 2.4. Embedded Memory Modes.....................................................................................29 2.4.1. Embedded Memory Configurations for Single-port Mode................................ 30 2.4.2. Embedded Memory Configurations for Dual-port Modes.................................31 2.5. Embedded Memory Clocking Modes........................................................................ 32 2.5.1. Clocking Modes for Each Memory Mode....................................................... 32 2.5.2. Asynchronous Clears in Clocking Modes...................................................... 33 2.5.3. Output Read Data in Simultaneous Read/Write.............................................33 2.5.4. Independent Clock Enables in Clocking Modes..............................................33 2.6. Parity Bit in Embedded Memory Blocks....................................................................33 2.7. Byte Enable in Embedded Memory Blocks................................................................33 2.7.1. Byte Enable Controls in Memory Blocks.......................................................34 2.7.2. Data Byte Output.....................................................................................34 2.7.3. RAM Blocks Operations............................................................................. 34 2.8. Memory Blocks Packed Mode Support..................................................................... 35 2.9. Memory Blocks Address Clock Enable Support..........................................................35 2.10. Memory Blocks Asynchronous Clear...................................................................... 36 2.11. Memory Blocks Error Correction Code Support....................................................... 37 2.11.1. Error Correction Code Truth Table............................................................. 38 2.12. Embedded Memory Blocks in Intel Arria 10 Devices Revision History......................... 38 ® ® Intel Arria 10 Core Fabric and General Purpose I/Os Handbook Send Feedback 2 Contents 3. Variable Precision DSP Blocks in Intel Arria 10 Devices................................................ 40 3.1. Supported Operational Modes in Intel Arria 10 Devices............................................. 40 3.1.1. Features................................................................................................. 42 3.2. Resources...........................................................................................................43 3.3. Design Considerations.......................................................................................... 44 3.3.1. Operational Modes................................................................................... 45 3.3.2. Internal Coefficient and Pre-Adder for Fixed-Point Arithmetic......................... 46 3.3.3. Accumulator for Fixed-Point Arithmetic....................................................... 46 3.3.4. Chainout Adder........................................................................................46 3.4. Block Architecture................................................................................................46 3.4.1. Input Register Bank................................................................................. 48 3.4.2. Pipeline Register...................................................................................... 51 3.4.3. Pre-Adder for Fixed-Point Arithmetic........................................................... 52 3.4.4. Internal Coefficient for Fixed-Point Arithmetic.............................................. 52 3.4.5. Multipliers...............................................................................................52 3.4.6. Adder.....................................................................................................52 3.4.7. Accumulator and Chainout Adder for Fixed-Point Arithmetic........................... 53 3.4.8. Systolic Registers for Fixed-Point Arithmetic................................................ 53 3.4.9. Double Accumulation Register for Fixed-Point Arithmetic............................... 54 3.4.10. Output Register Bank..............................................................................54 3.5. Operational Mode Descriptions...............................................................................54 3.5.1. Operational Modes for Fixed-Point Arithmetic............................................... 55 3.5.2. Operational Modes for Floating-Point Arithmetic........................................... 61 3.6. Variable Precision DSP Blocks in Intel Arria 10 Devices Revision History.......................68 4. Clock Networks and PLLs in Intel Arria 10 Devices....................................................... 70 4.1. Clock Networks....................................................................................................70 4.1.1. Clock Resources in Intel Arria 10 Devices.................................................... 71 4.1.2. Hierarchical Clock Networks.......................................................................73 4.1.3. Types of Clock Networks........................................................................... 75 4.1.4. Clock Network Sources............................................................................. 78 4.1.5. Clock Control Block.................................................................................. 79 4.1.6. Clock Power Down....................................................................................82 4.1.7. Clock Enable Signals................................................................................ 82 4.2. Intel Arria 10 PLLs............................................................................................... 83 4.2.1. PLL Usage...............................................................................................85 4.2.2. PLL Architecture.......................................................................................85 4.2.3. PLL Control Signals.................................................................................. 86 4.2.4. Clock Feedback Modes.............................................................................. 86 4.2.5. Clock Multiplication and Division.................................................................87 4.2.6. Programmable Phase Shift........................................................................ 88 4.2.7. Programmable Duty Cycle......................................................................... 89 4.2.8. PLL Cascading........................................................................................