PDP-11/34 system user's manual EK-11034-UG-001 PDP-11/34 system user's manual digital equipment corporation • maynard, massachusetts 1st Edition, July 1977 Copyright © 1977 by Digital Equipment Corporation The material in this manual is for informational purposes and is subject to change without notice. Digital Equipment Corporation assumes no respon· sibility for any errors which may appear in this manual. Printed in U.S.A. This document was set on DIGITAL's DECset-8000 computerized typesetting system. The following are trademarks of Digital Equipment Corporation, Maynard, Massachusetts: DEC DECtape PDP DECCOMM DECUS RSTS DECsystem.IO DIGITAL TYPESET·8 DECSYSTEM·20 MASS BUS TYPESET· I I UNIBUS 7/80-14 CONTENTS Page CHAPTER 1 INTRODUCTION 1.1 SCOPE ..... 1-1 1.2 SYSTEM DESCRIPTION 1-2 1.2.1 Unibus ...... 1-3 1.2.2 KDll-E (EA) Central Processor 1-3 1.2.3 Operator's Console ..... 1-4 1.2.4 M9301 Bootstrap/Terminator 1-5 1.2.5 M9302 Terminator . 1-6 1.2.6 Memory .......... 1-7 1.2.7 Mounting Box, Backplane, and Power Supply 1-9 1.2.8 Optional Equipment 1-11 1.3 RELA TED LITERATURE ........... 1-14 CHAPTER 2 OPERATION 2.1 OPERATOR'S CONSOLE (KY11-LA) 2-1 2.1.1 Console Switches . 2-1 2.1.2 Console Indicators ...... 2-3 2.1.3 Console Emulator ...... 2-3 2.1.3.1 Entry Into the Console Emulator 2-4 2.1.3.2 Register Printout ....... 2-4 2.1.3.3 Console Emulator Functions 2-5 . 2.1.3.4 Examples of Console Emulator Operation 2-6 2.1.3.5 Booting from Peripheral Devices 2-7 2.1.3.6 Possible Operator Errors 2-8 2.2 PROGRAMMER'S CONSOLE (KYII-LB) 2-10 2.2.1 KYII-LB Controls and Indicators 2-10 2.2.2 Notes on Operation ....... 2-12 2.2.3 Examples of Programmer's Console Operation 2-13 CHAPTER 3 FUNCTIONAL SYSTEM DESCRIPTION 3.1 GENERAL 3-1 3.1.1 Halt-Continue Function 3-1 3.1.2 Boot-Initialize Function 3-5 3.1.3 Power-Up Reboot Enable Feature 3-5 3.1.4 Sack Turnaround Feature 3-5 3.2 KY11-LA DETAILED DESCRIPTION 3-5 3.2.1 HALT/CONT Switch 3-6 3.2.2 BOOT/INIT Switch 3-8 3.2.3 DC Power Switch 3-9 3.2.4 Indicators 3-9 iii CONTENTS (CONT) Page 3.3 M930l BOOTSTRAP/ROM FIRMWARE · 3-10 3.3.1 Basic CPU Diagnostics · 3-10 3.3.2 Register Display Routine . · 3-12 3.3.3 Memory-Modifying Diagnostics · 3-12 3.3.4 Bootstrap Programs ..... · 3-14 CHAPTER 4 CONFIGURATION 4.1 GENERAL 4-1 4.2 BACKPLANE ... 4-1 4.2.1 Physical Description 4-1 4.2.2 Electrical Connections 4-1 4.2.2.1 Power ..... 4-1 4.2.2.2 Backplane Signal Connections 4-6 4.2.3 Module Placement · 4-10 4.3 SWITCHES AND JUMPERS · 4-15 4.3.1 KD 11-E Processor · 4-15 4.3.2 KD 11-EA Processor 4-15 4.3.3 M9301 Bootstrap/Terminator 4-15 4.3.4 DL1l-W Serial Line Interface and Real-Time Clock 4-19 4.3.4.1 Device Address 4-20 4.3.4.2 Vector Address ..... 4-21 4.3.4.3 Baud Rate ....... · 4-21 4.3.4.4 20-mA Current Loop Mode · 4-22 4.3.4.5 Data Format ...... · 4-22 4.3.4.6 DL1l-W Compatibility Switches 4-23 4.3.5 MSll-EP, MS11-FP, and MSll-JP MOS Memory · 4-24 4.3.6 MM ll-CP Core Memory · 4-26 4.3.7 MM11-DP Core Memory 4-26 4.3.8 M7850 Parity Controller · 4-27 CHAPTERS INSTALLATION 5.1 GENERAL ...... 5-1 5.2 SITE CONSIDERATIONS 5-1 5.2.1 Humidity and Temperature 5-1 5.2.2 Air-Conditioning .. 5-2 5.2.3 Acoustical Damping 5-2 5.2.4 Lighting ..... 5-2 5.2.5 Special Mounting Conditions 5-2 5.2.6 Static Electricity ..... 5-2 5.3 ELECTRICAL REQUIREMENTS 5-2 5.3.1 System Grounding '" 5-4 5.3.2 Specifications Summary 5-5 5.4 UNPACKING ....... 5-6 5.5 MODULE UTILIZATION IN TYPICAL SYSTEMS 5-9 iv CONTENTS (CONT) Page 5.6 INITIAL INSPECTION ........... 5-10 5.7 TYPICAL SWITCH SETTINGS OF MODULES 5-13 5.B FIRST-TIME START-UP PROCEDURE 5-21 5.B.I Check of Standby Operation 5-23 CHAPTER 6 TROUBLESHOOTING 6.1 PDP-I 1/34 CHARACTERISTICS SUMMARY 6-1 6.1.1 Operation (KY II-LA) ..... 6-1 6.1.2 Operation (KYll-LB) ..... 6-1 6.1.3 Installation ........... 6-2 6.2 TROUBLESHOOTING PROCEDURES 6-2 6.2.1 Quick Verification Routine 6-2 6.2.2 Troubleshooting Flowcharts and Explanations 6-6 APPENDIX A KYI1-LB MAINTENANCE MODE OPERATION APPENDIX B EXTENDED ADDRESSING APPENDIX C SUMMARY OF EQUIPMENT SPECIFICATIONS FIGURES Figure No. Title Page I-I PDP-I 1/34 Computer System . I-I 1-2 System Block Diagram . 1-2 1-3 KDII-E Central Processor Unit (M7265 Module) 1-3 1-4 KDII-E Central Processor Unit (M7266 Module) 1-4 1-5 Operator's Console ........ 1-5 1-6 M9301 Bootstrap/Terminator Module 1-6 1-7 M9302 Tenninator Module 1-7 I-B MSl1-1P MOS Memory Module I-B 1-9 MMII-CP Core Memory Module 1-9 1-10 MMll-DP Core Memory Module 1-10 I-II M7B50 Parity Controller I-II 1-12 DL1I-W Serial Line Interface and Real-Time Clock 1-12 1-13 KYII-LB Console and Interface Module 1-13 2-1 PDP-I 1/34 Operator's Console ......... 2-1 2-2 PDP-l 1/34 Programmer's Console ........ 2-10 3-1 PDP-ll/34 System Interconnections (BAII-L Mounting Box) 3-3 3-2 PDP-l 1/34 System Interconnections (BAl1-K Mounting Box) . 3-4 v FIGURES (CONT) Figure No. Title Page 3~3 M9302 Sack Turnaround Logic 3-6 3-4 HALT/CaNT Switch Logic 3-7 3-5 BOOT /INIT Switch Logic 3-8 3-6 DC Power Switch 3-9 3-7 DC ON Indicator 3-9 3-8 BATT Indicator . 3-9 4-1 PDP-11/34 Backplanes 4-2 4-2 Mate-N-Lok Connector Pin Locations (Viewed from Wire Side) 4-3 4-3 3M Connector Pin Locations (Viewed from Pin Side) 4-6 4-4 Standard and Modified Unibus Pin Designations 4-8 4-5 SPC Pin Designations 4-9 4-6 NPG Signal Path . 4-10 4-7 BG Signal Path (BG4 Line) 4-11 4-8 Module Placement .... 4-13 4-9 DL11-W (M7856) Switch Locations 4-19 4-10 DL11-W Device Address Selection . 4-20 4-11 DL11-W Vector Address Selection 4-21 5-1 Connector Specifications for BA11-L and BA11-K Boxes 5-3 5-2 Connector Specifications for 861-B and 861-C Power Controllers 5-4 5-3 Packaging ofPDP-11/34 [26.3 cm (l0-1/2 inch Box)] 5-7 5-4 Packaging of PDP-11/34 [13.3 cm (5-1/4 inch Box)] 5-8 5-5 PDP-11/34 Module Utilization ......... 5-9 5-6 Computer Subassemblies of BA11-L Mounting Box 5-10 5-7 Computer Subassemblies of BA11-K Mounting Box 5-11 5-8 Backplane Connectors .. 5-12 5-9 Typical Jumper Placement and Switch Settings of Modules 5-13 6-1 Action 1 6-9 6-2 Action 2 6-11 6-3 Action 3 6-12 6-4 Action 4 6-13 6-5 Action 5 6-13 6-6 Action 6 6-14 6-7 Action 7 6-14 vi TABLES Table No. Title Page 2-1 Bootstrap Routine Codes for M930l-YA and M9301-YB 2-7 2-2 Bootstrap Routine Codes for M930l-YF 2-8 2-3 Load, Examine, Deposit, and Start Errors .. 2-9 3-1 Priority Service Order ................. 3-1 4-1 Power Connector Signal Assignments for DDll-PK and DDll-DK 4-3 4-2 Power Connector Signal Assignments for DDll-CK 4-5 4-3 10-Pin 3M Connector Signal Designations . 4-7 4-4 M930l-YA ROM Starting Address Selection 4-16 4-5 M930l-YB ROM Starting Address Selection 4-17 4-6 M930 1-YF ROM Starting Address Selection 4-17 4-7 DL1l-W Switch Functions ....... 4-23 4-8 Switch Settings for MS 11 Address Assignments 4-25 4-9 MM ll-CP Memory Address Selection 4-26 4-10 MM ll-DP Memory Address Selection 4-26 5-1 PDP-II /34 Diagnostics ...... 5-24 vii CHAPTER 1 INTRODUCTION 1.1 SCOPE This manual is intended to provide an introduction to the PDP-ll/34 computer system and present the information required by the user for configuration, installation, operation, familiarization with system components, and limited troubleshooting procedures. The basic PDP-11/34 (Figure 1-1) includes a simple operator's console which does not contain a switch register and light display. Communication between the user and computer is implemented via the system terminal. A special bootstrap/terminator module allows the terminal to simulate the func­ tion of a traditional programmer's console. '" & 8141-21 Figure 1-1 PDP-ll/34 Computer System A version of the 11/34, designated 11/34A, was developed to accommodate a floating point option (FPII-A).