Vivado Design Suite User Guide Programming and Debugging UG908 (v2019.1) May 22, 2019 Revision History The following table shows the revision history for this document. Section Revision Summary 05/22/2019 Version 2019.1 Configuration Memory Support Replaced Configuration Memory Support Tables. Bus Plot Viewer Added new section on Bus Plot Viewer. High Bandwidth Memory (HBM) Monitor Added new section on High Bandwidth (HBM) Monitor. Vivado Programming and DebuggingSend Feedback 2 UG908 (v2019.1) May 22, 2019 www.xilinx.com Table of Contents Revision History . 2 Chapter 1: Introduction Getting Started. 8 Debug Terminology . 9 Chapter 2: Vivado Lab Edition Installation . 12 Using the Vivado Lab Edition . 13 Vivado Lab Edition Project . 14 Programming Features . 18 Debug Features . 18 Chapter 3: Generating the Bitstream Changing the Bitstream File Format Settings. 20 Changing Device Configuration Bitstream Settings . 20 Chapter 4: Programming the FPGA Device Opening the Hardware Manager . 22 Opening Hardware Target Connections . 23 Connecting to a Hardware Target Using hw_server . 24 Opening a New Hardware Target . 24 Troubleshooting a Hardware Target. 27 Associating a Programming File with the Hardware Device . 29 Programming the Hardware Device . 29 Closing the Hardware Target. 33 Closing a Connection to the Hardware Server . 34 Reconnecting to a Target Device with a Lower JTAG Clock Frequency . 34 Connecting to a Server with More Than 32 Devices in a JTAG Chain . 36 Chapter 5: Remote Debugging in Vivado Using Vivado Hardware Server to Debug Over Ethernet . 37 Xilinx Virtual Cable (XVC) . 38 Vivado Programming and DebuggingSend Feedback 3 UG908 (v2019.1) May 22, 2019 www.xilinx.com Chapter 6: Programming Configuration Memory Devices Generate Bitstreams for use with Configuration Memory Devices . 51 Creating a Configuration Memory File . 52 Creating a Configuration Memory File for SPI Dual Quad (x8) Devices . 53 Connect to the Hardware Target in Vivado . 55 Adding a Configuration Memory Device . 55 Programming a Configuration Memory Device . 58 Booting the Device. 60 Configuration Failures in Master Mode . 62 Chapter 7: Advanced Programming Features Readback and Verify . 63 Generating Encrypted and Authenticated Files for 7 Series Devices . 67 Generating Encrypted and Authenticated Files for UltraScale and UltraScale+ . 69 Programming the AES Key for 7 Series Devices . 74 Programming the AES Key for UltraScale and UltraScale+ Devices . 76 eFUSE Register Access and Programming . 79 Cable Support for eFUSE Programming . 79 eFUSE Register Access and Programming for 7 Series Devices. 80 eFUSE Register Access and Programming for UltraScale and UltraScale+ Devices . 85 eFUSE NKZ File . 92 System Monitor . 93 Chapter 8: Serial Vector Format (SVF) File Programming Creating an SVF Target. 95 Adding Devices to an SVF Target . 99 Adding Configuration Memory Parts to Xilinx Devices . 103 Operations on the SVF Chain . 105 Writing SVF Files . 108 Executing SVF Files. 110 Chapter 9: Debugging the Design RTL-Level Design Simulation . 111 Post-Implemented Design Simulation . 111 In-System Logic Design Debugging . 112 In-System Serial I/O Design Debugging . 112 Chapter 10: In-System Logic Design Debugging Flows Probing the Design for In-System Debugging. 113 Using the Netlist Insertion Debug Probing Flow . 114 Vivado Programming and DebuggingSend Feedback 4 UG908 (v2019.1) May 22, 2019 www.xilinx.com HDL Instantiation Debug Probing Flow Overview . 130 Using the HDL Instantiation Debug Probing Flow . 131 Debug Flow in IPI . 141 Implementing the Design Containing the Debug Cores . 144 ILA Core and Timing Considerations. 144 Debug Cores Clocking Guidelines . 145 Adding Vivado Debug Cores to a Partial Reconfiguration Design . 149 Chapter 11: Debugging Logic Designs in Hardware Using Vivado Logic Analyzer to Debug the Design. 150 Connecting to the Hardware Target and Programming the FPGA Device . 150 Vivado Hardware Manager Dashboards . 151 Setting up the ILA Core to Take a Measurement. 162 Writing ILA Probes Information . 191 Reading ILA.