Embedded Intel486™ Processor Family Developer’s Manual Release Date: October 1997 Order Number: 273021-001 The Intel486™ processors may contain design defects known as errata which may cause the products to deviate from published specifications. Currently characterized errata are avail- able on request. Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or oth- erwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel retains the right to make changes to specifications and product descriptions at any time, without notice. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. *Third-party brands and names are the property of their respective owners. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 5937 Denver, CO 80217-9808 or call 1-800-548-4725 or visit Intel’s website at http:\\www.intel.com Copyright © INTEL CORPORATION, October 1997 CONTENTS CHAPTER 1 GUIDE TO THIS MANUAL 1.1 MANUAL CONTENTS .................................................................................................. 1-1 1.2 NOTATION CONVENTIONS ........................................................................................ 1-3 1.3 SPECIAL TERMINOLOGY ........................................................................................... 1-4 1.4 ELECTRONIC SUPPORT SYSTEMS .......................................................................... 1-5 1.4.1 FaxBack Service ...................................................................................................... 1-5 1.4.2 World Wide Web ...................................................................................................... 1-5 1.5 TECHNICAL SUPPORT ............................................................................................... 1-5 1.6 PRODUCT LITERATURE ............................................................................................. 1-6 1.6.1 Related Documents ................................................................................................. 1-6 CHAPTER 2 EMBEDDED Intel486™ PROCESSOR OVERVIEW 2.1 PROCESSOR FEATURES ........................................................................................... 2-2 2.2 Intel486™ PROCESSOR PRODUCT OPTIONS .......................................................... 2-4 2.2.1 Operating Modes and Compatibility ......................................................................... 2-5 2.3 SYSTEMS APPLICATIONS .......................................................................................... 2-6 2.3.1 Embedded Personal Computers .............................................................................. 2-6 2.3.2 Embedded Controllers ............................................................................................. 2-7 CHAPTER 3 ARCHITECTURAL OVERVIEW 3.1 INTERNAL ARCHITECTURE ....................................................................................... 3-1 3.1.1 Overview .................................................................................................................. 3-1 3.1.2 Bus Interface Unit (BIU) ........................................................................................... 3-6 3.1.3 Data Transfers ......................................................................................................... 3-7 3.1.4 Write Buffers ............................................................................................................ 3-7 3.1.5 Locked Cycles .......................................................................................................... 3-8 3.1.6 I/O Transfers ............................................................................................................ 3-8 3.2 CACHE UNIT ................................................................................................................ 3-9 3.2.1 Cache Structure ....................................................................................................... 3-9 3.2.2 Cache Updating ..................................................................................................... 3-11 3.2.3 Cache Replacement .............................................................................................. 3-11 3.2.4 Cache Configuration .............................................................................................. 3-11 3.3 INSTRUCTION PREFETCH UNIT .............................................................................. 3-13 3.4 INSTRUCTION DECODE UNIT .................................................................................. 3-13 3.5 CONTROL UNIT ......................................................................................................... 3-14 3.6 INTEGER (DATAPATH) UNIT .................................................................................... 3-14 3.7 FLOATING-POINT UNIT ............................................................................................ 3-14 3.7.1 IntelDX2™ and IntelDX4™ Processor On-Chip Floating-Point Unit ...................... 3-14 3.8 SEGMENTATION UNIT .............................................................................................. 3-15 iii EMBEDDED Intel486™ PROCESSOR FAMILY DEVELOPER’S MANUAL 3.9 PAGING UNIT ............................................................................................................ 3-16 3.9.1 Instruction Pipelining .............................................................................................. 3-17 3.10 SYSTEM ARCHITECTURE ........................................................................................ 3-18 3.10.1 Single Processor System ....................................................................................... 3-19 3.10.2 Loosely Coupled Multi-Processor System ............................................................. 3-20 3.10.3 System Components .............................................................................................. 3-21 3.10.4 External Cache ...................................................................................................... 3-22 3.11 MEMORY ORGANIZATION ....................................................................................... 3-23 3.11.1 Address Spaces ..................................................................................................... 3-23 3.11.2 Segment Register Usage ....................................................................................... 3-24 3.12 I/O SPACE .................................................................................................................. 3-25 3.13 ADDRESSING MODES .............................................................................................. 3-26 3.13.1 Addressing Modes Overview ................................................................................. 3-26 3.13.2 Register and Immediate Modes ............................................................................. 3-26 3.13.3 32-Bit Memory Addressing Modes ......................................................................... 3-26 3.13.4 Differences Between 16- and 32-Bit Addresses .................................................... 3-29 3.14 Data Formats .............................................................................................................. 3-30 3.14.1 Data Types ............................................................................................................. 3-30 3.14.1.1 Unsigned Data Types ........................................................................................ 3-30 3.14.1.2 Signed Data Types ............................................................................................ 3-30 3.14.1.3 BCD Data Types ............................................................................................... 3-30 3.14.1.4 Floating-Point Data Types ................................................................................. 3-31 3.14.1.5 String Data Types ............................................................................................. 3-31 3.14.1.6 ASCII Data Types ............................................................................................. 3-31 3.14.1.7 Pointer Data Types ........................................................................................... 3-34 3.14.2 Little Endian vs. Big Endian Data Formats ............................................................. 3-34 3.15 INTERRUPTS ............................................................................................................. 3-35 3.15.1 Interrupts and Exceptions ...................................................................................... 3-35 3.15.2 Interrupt Processing ............................................................................................... 3-36 3.15.3 Maskable Interrupt ................................................................................................