Intel® IXP43X Product Line of Network Processors Datasheet Product Features This document describes the features of the Intel® IXP43X Product Line of Network Processors. Refer to Section 1.0 for a complete list of all the features. Some of these features require enabling software supplied by Intel. Refer to the Intel® IXP400 Software Programmer’s Guide for information on features that are currently enabled. These features do not require These features require enabling enabling software software. For information on ® Intel XScale Processor — Up to features that are currently enabled ® 667 MHz see the Intel IXP400 Software Programmer’s Guide. PCI v. 2.2 32-bit 33 MHz (Host/ Option) Encryption/Authentication (AES/ AES-CCM/3DES/DES/SHA-1/SHA-256/ Two USB v2.0 Host Controller SHA-384/SHA-512/MD-5) DDRI-266 MHz/DDRII-400MHz SDRAM Interface One High-Speed Serial Interface Two Network Processor Engines Slave Interface Expansion bus Up to two MII Interfaces One UART One UTOPIA Level 2 Interface Internal Bus Performance Monitoring Unit IEEE-1588 Hardware Assist 16 GPIO Four Internal Timers Synchronous Serial Protocol (SSP) Port Packaging —460-Pin PBGA — Commercial Temperature — Lead-Free Support Typical Applications SOHO-Small Business/ Residential VoIP Router Modular Router Video Phone Wireless Gateway (802.11a/b/g) Security Gateway/Router Network-Attached Storage Network Printers Wired/Wireless RFID Readers Wireless Media Gateway Digital Media Adapter IP Set Top box Document Number: 316842; Revision: 003US December 2008 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. 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Intel® IXP43X Product Line of Network Processors Datasheet December 2008 2 Document Number: 316842; Revision: 003US Contents Contents 1.0 Features of the Intel® IXP43X Product Line of Network Processors...........................9 1.1 Product Line Features ..........................................................................................9 1.2 Model Specific Features...................................................................................... 12 2.0 About This Document .............................................................................................. 13 3.0 Functional Overview ................................................................................................ 13 3.1 Key Functional Units .......................................................................................... 19 3.1.1 Network Processor Engines (NPEs)............................................................ 19 3.1.2 Internal Bus .......................................................................................... 20 3.1.2.1 North AHB ............................................................................... 20 3.1.2.2 South AHB ............................................................................... 21 3.1.2.3 Memory Port Interface............................................................... 21 3.1.2.4 APB Bus .................................................................................. 21 3.1.3 MII Interfaces........................................................................................ 22 3.1.4 UTOPIA Level 2 Interface ........................................................................ 22 3.1.5 USB Version 2.0 Host Interface ................................................................ 22 3.1.6 PCI Controller ........................................................................................ 23 3.1.7 DDRII/DDRI Memory Controller................................................................ 23 3.1.8 Expansion Interface................................................................................ 26 3.1.9 High-Speed Serial Interface ..................................................................... 26 3.1.10 UART Interface ...................................................................................... 27 3.1.11 GPIO .................................................................................................... 27 3.1.12 Internal Bus Performance Monitoring Unit (IBPMU) ..................................... 28 3.1.13 Interrupt Controller ................................................................................ 28 3.1.14 Timers .................................................................................................. 28 3.1.15 IEEE-1588 Hardware Assist ..................................................................... 29 3.1.16 Synchronous Serial Port Interface............................................................. 29 3.1.17 AES/DES/SHA/MD-5 ............................................................................... 29 3.1.18 Queue Manager...................................................................................... 30 3.2 Intel XScale® Processor ..................................................................................... 30 3.2.1 Super Pipeline........................................................................................ 31 3.2.2 Branch Target Buffer .............................................................................. 32 3.2.3 Instruction Memory Management Unit ....................................................... 32 3.2.4 Data Memory Management Unit ............................................................... 33 3.2.5 Instruction Cache ................................................................................... 33 3.2.6 Data Cache ........................................................................................... 34 3.2.7 Mini-Data Cache..................................................................................... 34 3.2.8 Fill Buffer and Pend Buffer ....................................................................... 34 3.2.9 Write Buffer........................................................................................... 34 3.2.10 Multiply-Accumulate Coprocessor ............................................................. 35 3.2.11 Performance Monitoring Unit.................................................................... 35 3.2.12 Debug Unit............................................................................................ 36 4.0 Package Information ............................................................................................... 36 4.1 Functional Signal Definitions ............................................................................... 36 4.1.1 Pin Types .............................................................................................. 37 4.1.2 Pin Description Tables............................................................................. 37 4.2 Package Description .......................................................................................... 60 4.3 Signal-Pin Description