Si MOSFET Roadmap for 22nm and beyond December 1６, 2009 Jadavpur University @ Kolkata, India Hiroshi Iwai Tokyo Institute of Technology 1 Outline 1. Scaling 2. ITRS Roadmap 3. Voltage Scaling/ Low Power and Leakage 4. SRAM Cell Scaling 5.Roadmap for further future 2 1. Scaling 3 Scaling Method: by R. Dennard in 1974 1 Wdep: Space Charge Region (or Depletion Region) Width 1 1 SDWdep has to be suppressed 1 Otherwise, large leakage Wdep between S and D I Leakage current Potential in space charge region is high, and thus, electrons in source are 0 attracted to the space charge region. 0 V 1 K=0.7 X , Y, Z :K, V :K, Na : 1/K for By the scaling, Wdep is suppressed in proportion, example and thus, leakage can be suppressed. K Good scaled I-V characteristics K K Wdep V/Na K Wdep I I : K : K 0 0K V 4 Downscaling merit: Beautiful! Geometry & L , W g g K Scaling K : K=0.7 for example Supply voltage Tox, Vdd Id = vsatWgCo (Vg‐Vth) Co: gate C per unit area Drive current I d K –1 ‐1 ‐1 in saturation Wg (tox )(Vg‐Vth)= Wgtox (Vg‐Vth)= KK K=K Id per unit Wg Id/µm 1 Id per unit Wg = Id / Wg= 1 Gate capacitance Cg K Cg = εoεoxLgWg/tox KK/K = K Switching speed τ K τ= CgVdd/Id KK/K= K Clock frequency f 1/K f = 1/τ = 1/K Chip area Achip α α: Scaling factor In the past, α>1 for most cases Integration (# of Tr) N α/K2 N α/K2 = 1/K2 , when α=1 Power per chip P α fNCV2/2 K‐1(αK‐2)K (K1 )2= α = 1, when α=1 5 2 Generations k= 0.72 =0.5 and α =1 Single MOFET Vdd 0.5 Lg 0.5 Id 0.5 Cg 0.5 P (Power)/Clock 0.53 = 0.125 τ (Switching time) 0.5 Chip N (# of Tr) 1/0.52 = 4 f (Clock) 1/0.5 = 2 P (Power) 1 6 - The concerns for limits of down-scaling have been announced for every generation. - However, down-scaling of CMOS is still the ‘royal road’* for high performance and low power. - Effort for the down-scaling has to be continued by all means. *Euclid of Alexandria (325BC?-265BC?) ‘There is no royal road to Geometry’ Mencius (Meng-zi), China (372BC?-289BC?) (Rule of right vs. Rule of military) 7 Actual past downscaling trend until year 2000 10 2 Past 30 years scaling Minimum logic Vdd (V) 10 3 10 1 Merit: N, f increase M 2 ） z) PU （mm H L ize (M X g (µm ip s cy 10 0 j (µm ) ch uen Demerit: P increase ) 10 1 req Id/µm k f (mA/µm) loc ) c S (W s -1 IP r or 10 t M ist ox (µm owe ns ) -1 p ra V scaling insufficient 10 f t dd -2 r o 10 be m Nu 10 -3 10 -3 Additional significant 1970 1980 1990 2000 1970 1980 1990 2000 increase in Source. Iwai and S. Ohmi, Microelectronics Reliability 42 (2002), pp.1251-1268 I , f, P Change in 30 years d Ideal Real Ideal Real Ideal Real scaling Change scaling Change scaling Change ‐2 Lg K 10 –2 ‐1 –2 ‐2 Id K (10 ) 10 f 1/K(10 2) 103 tox K(10 ) 10 –2 10‐1 I /µm 1 101 Vdd K(10 ) d P α(10 1) 105 2 5 4 2 Achip α 101 N α/K (10 ) 10 = fαNCV Vd scaling insufficient, α increased N, Id, f, P increased significantly 8 - Now, power and/or heat generation are the limiting factors of the down-scaling - Supply voltage reduction is becoming difficult, because Vth cannot be decreased any more, as described later. - Growth rate in clock frequency and chip area becomes smaller. 9 2. ITRS Roadmap (for 22 nm CMOS logic) 10 What is a roadmap? What is ITRS? Roadmap: Prediction of future technologies ITRS: International Technology Roadmap for Semiconductors made by SIA (Semiconductor Industry Association with Collaboration with Japan, Europe, Korea and Taiwan) 1000 100 Gateゲート長 Gateゲート絶縁膜厚 length oxide 1992 100 10 1994 thickness 2001 1992 40nm 2003 1997 1994 1999 1999 EOTEOT [nm] [nm] 1.5nm 2001 10 1 1997 2003 2005 2005 PhysicalPhysical Gate Gate Length Length [nm] [nm] 1 0.1 1995 2005 2015 1995 2005 2015 11 1992 -1997:NTRS (National Technology Roadmap) 1998 - : ITRS (International Technology Roadmap) 2008 ITRS update 2007 ITRS 2006 ITRS update ITRS Roadmap does change every year! 2007 Edition 2003 Edition 2006 Update 2002 Update 2005 Edition 2001 Edition 2004 Update 2000 Update http://www.itrs.net/reports.html 13 HP, LOP, LSTP for Logic CMOS 100 e) 10 1 Operation Frequency (a.u.) Subthreshold Leakage (A/µm) Source: 2007 ITRS Winter Public Conf. 14 What does ‘45 nm’ mean in 45 nm CMOS Logic? ‘XX nm CMOS Technology ITRS 2008 Update Commercial Logic CMOS products for High Performance Logic Physical Technology Starting Year Half Pitch st Gate Length name Year (1 Metal) 45 nm 2007 2007 68 nm 32 nm 2008 59 nm 29 nm 32 nm 2009?2009 52 nm 27 nm 2010 45 nm 24 nm ‘XX nm’ CMOS Logic Technology: - In general, there is no common corresponding parameter with ‘XX nm’ in ITRS table, which stands for ‘XX nm’ CMOS. 15 What does ‘45 nm’ mean in 45 nm CMOS Logic? 8µm Æ 6µm Æ 4µm Æ 3µm Æ 2µm Æ 1.2µm Æ 0.8µm Æ 0.5µm - Originally, ‘XX’ means lithography resolution. - Thus, ‘XX’ was the gate length, and half pitch of lines - ‘XX’ had shrunk 0.7 in 3 years in average (0.5 in 6 years) those days. Logic 1st Metal Half Pitch 16 What does ‘45 nm’ mean in 45 nm CMOS Logic? Æ 350nm Æ 250nm Æ 180nm Æ 130nm Æ 90nm Æ 65nm Æ 45nm -‘XX’ values were established by NTRS* and ITRS with the term of ‘Technology Node**’ and ‘Cycle***’ using typical ‘half pitch value’. - The gate length of logic CMOS became smaller with one or two generations from the half pitch, and ‘XX’ names ahead of generations have been used for logic CMOS. Resist Ashing Resist - Memory still keeps the half pitch as the value of ‘XX’ 17 For example, Typical Half Pitches at ITRS 2007 Too aggressive HP=45nm shrink 2010 Lg=18nm Resist Ashing Resist Source: 2008 ITRS Summer Public Conf. 18 Physical gate length in past ITRSmance was too logic aggressive. will shift by 3-5 yrs. The dissociation from commercial product prediction will be adjusted. Physical gate length of High-Perfor Correspond to 32nm 22nm Logic CMOS 45nm X0.71 / 3 Year X0.71 / 3 Year ITRS 2007 Print Lg 2008 Update Print Lg 2008Update 32nm 27nm 22nm 2008 Update Phys. Lg X0.71 / 3.8 Year 25nm 20nm 16nm ITRS 2007 Phys. Lg X0.71 / 3 Year 5 year shift ITRS2007 3 year shift 19 Summer Public Conf. Source: 2008 ITRS EOT and Xj shift backward, corresponding to Lg shift EOT: 0.55 nm Æ 0.88 nm, Xj: 8 nm Æ 11 nm @ 22nm CMOS Likely in 2008 Update Correspond to 22nm Source: 2008/ ITRS Summer Public Conf. Likely in 2008 Update Likely in 2008 Update 8 Likely in 2008 Update non-steady trend filled in for metal gate EOT for 2009/10 corrected based on latest conference presentations 20 What does ‘22 nm’ mean in 22 nm CMOS Logic? ‘XX nm CMOS Technology ITRS (Likely in 2008 Update) Commercial Logic CMOS products for High Performance Logic Physical Technology Starting Year Half Pitch st Gate Length name Year (1 Metal) 45 nm 2007 2007 68 nm 32 nm 2008 59 nm 29 nm 32 nm 2009?2009 52 nm 27 nm 2010 45 nm 24 nm 22 nm 2011?~ 2011 40 nm 22 nm 2012? 2012 36 nm 20 nm 16 nm 2013?~ 2013 32 nm 18 nm 2014? 2014 29 nm 16 nm Source: 2008 ITRS Summer Public Conf. From ITRS2008 Update, maybe XX nm stands for the physical Gate length 21 Clock frequency does not increase aggressively anymore. Even decreased! Advantage in SISC Era for ‘out of order’ Multi Core Advantage in RISC Clock ≠ Simple configuration Performance Source: Mitsuo Saito, Toshiba 22 ITRS2007 Continued? Core Clock Cell Broadband Engine Frequency Chip Freq uen cy 6GHz capability Source: 2007 ITRS for SRAM Winter Public Conf. Source: IBM, Toshiba, Sony ISSCC2008 and 08 23 Max on chip frequency or ‘Core clock’ 001 ITRS2 ITRS2003 ITRS2005 15%/Year 8%/Y ITRS ear 2007 22 nm: 6 GHz? Source: 2008 ITRS Summer Public Conf. 24 Structure and technology innovation (ITRS 2007) Source: 2008 ITRS Summer Public Conf. 25 Timing of CMOS innovations shifts backward. Bulk CMOS has longer life now! Correspond to 22nm Logic CMOS Bulk extends 4 years! Multi G delays 4 years! Source: 2008 ITRS Summer Public Conf. 26 Wafer size (ITRS 2007) Correspond to 22nm Source: ITRS 2007 ?? Maybe delay?? 27 ITRS2008 Low-k Roadmap Update Correspond to 22nm Logic ITRS 2007 Update 2008 ITRS 2007 Update 2007 Source: 2008 ITRS Summer Public Conf. k value increases by 0.1 ~ 0.3 28 Historical Transition of ITRS Low-k Roadmap ITRS2003 ITRS2005 ITRS2007,8 ITRS2001 ITRS1999 Source: 2008 ITRS Summer Public Conf. 29 Roadmap towards 22nm technology and beyond - Physical gate length downsizing rate will be less aggressive. - Corresponding to the above, performance increase would slow down – Clock frequency, etc. - Introduction of innovative structures – UTB SOI and DG delayed, and bulk CMOS has longer life than predicted by previous ITRS roadmaps.