Freescale Semiconductor, Inc. DSP56100 16-BIT nc... DIGITAL SIGNAL PROCESSOR FAMILY MANUAL Freescale Semiconductor, I Motorola, Inc. Semiconductor Products Sector DSP Division 6501 William Cannon Drive, West Austin, Texas 78735-8598 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. nc... Order this document by DSP56100FM/AD Motorola reserves the right to make changes without further notice to any products herein to im- Freescale Semiconductor, I prove reliability, function or design. Motorola does not assume any liability arising out of the appli- cation or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not authorized for use as components in life support devices or systems intended for surgical implant into the body or intended to support or sustain life. Buyer agrees to notify Motorola of any such intended end use whereupon Motorola shall determine availability and suitability of its product or products for the use intended. Motorola and M are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Employment Oppor- tunity /Affirmative Action Employer. OnCEä is a trade mark of Motorola, Inc. ã Motorola Inc., 1994 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. SECTION 1 DSP56100 FAMILY INTRODUCTION nc... Freescale Semiconductor, I MOTOROLA DSP56100 FAMILY INTRODUCTION 1 - 1 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. SECTION CONTENTS 1.1 INTRODUCTION . 1-3 1.2 DSP56100 FAMILY FEATURES . 1-4 nc... Freescale Semiconductor, I 1 - 2 DSP56100 FAMILY INTRODUCTION MOTOROLA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. INTRODUCTION 1.1 INTRODUCTION The DSP56100 Family Manual (see Figure 1-1) provides a description of the components that are common to all DSP56100 family processors and includes a detailed description of the basic DSP56100 family instruction set. The DSP56156 User’s Manual and DSP56166 User’s Manual provide a brief overview of the core processor and a detailed descriptions of the memory and peripherals that are chip specific. 16-bit 16-bit 16-bit Products DSP56156 DSP56166 DSP561xx nc... DSP56100 Family Manuals Family Manual • architecture • instructions DSP56156 DSP56166 DSP561xx Device Manuals User’s Manual User’s Manual User’s Manual • peripherals • memories # DSP56156UM/AD # DSP56166UM/AD # DSP561xxUM/AD DSP56156 DSP56166 DSP561xx Specifications Technical Data Technical Data Technical Data • electrical # DSP56156/D # DSP56166/D # DSP561xx/D • mechanical Freescale Semiconductor, I Figure 1-1 DSP56100 Family Product Literature A DSP561xx User’s Manual and a DSP561xx Technical Data Sheet will be available for any future DSP56100 family member. MOTOROLA DSP56100 FAMILY INTRODUCTION 1 - 3 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. DSP56100 FAMILY FEATURES 1.2 DSP56100 FAMILY FEATURES The DSP56100 family consists of programmable CMOS 16-bit Digital Signal Processor core composed of a 16-bit arithmetic DATA ALU (DALU), Address Generation Unit (AGU), Program Controller Unit (PCU), and their associated DSP instruction set. Table 1-1 gives a description of the DSP Core features. Table 1-1 DSP Core Feature List • Up to 30 Million Instructions per Second (MIPS) at 60 MHz.– 33.3 ns instruction cycle • Single-cycle 16 x 16-bit parallel multiply-accumulate • 2 x 40-bit accumulators with extension byte • Fractional and integer arithmetic with support for multiprecision arithmetic • Highly parallel instruction set with unique DSP addressing modes • Nested hardware DO loops including infinite loops nc... • Two instruction LMS adaptive filter loop • Fast auto-return interrupts • Three external interrupt request pins • Three 16-bit internal data buses and three 16-bit internal address buses • Programmable access time on the external bus • On-chip peripheral registers memory mapped in data memory space • Off-chip peripheral space with programmable access time memory mapped in data memory space • Low power wait and stop modes • On-Chip Emulation (OnCE) for unobtrusive, processor speed independent debugging • Operating frequency down to DC • Single power supply • Low power (HCMOS) The block diagram of the core processor used in the DSP56100 family is shown in Figure 1-2. Freescale Semiconductor, I 1- 4 DSP56100 FAMILY INTRODUCTION MOTOROLA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. DSP56100 FAMILY FEATURES XAB1 XAB2 EXTERNAL ADDRESS ADDRESS ADDRESS GENERATION PAB BUS UNIT SWITCH ON-CHIP PERIPHERALS BOOTSTRAP PROGRAM DATA PORT A PORT HOST, SSI0, SSI, ROM RAM RAM BUS 8 TIMER, PI/O, CONTROL CODEC, ETC. XDB INTERNAL DATA DATA BUS SWITCH PDB EXTERNAL AND BIT DATA BUS MANIPULATION SWITCH UNIT GDB nc... EXTAL PROGRAM CONTROL UNIT CLOCK SXFC AND PLL PROGRAM PROGRAM PROGRAM DATA ALU CLKO ADDRESS DECODE INTERRUPT 16x16+40 - 40-BIT MAC GENERATOR CONTROLLER CONTROLLER TWO 40-BIT ACCUMULATORS OnCE 4 MODx/IRQx 16 BITS RESET HOST INTERFACE NOT PART OF THE CORE Figure 1-2 DSP56100 Family Core CPU Block Diagram The amount and type of on-chip memory varies from chip to chip within the family and so is not discussed here. However, the architecture allows up to 64K words each (128k total) of program memory and data memory to be addressed. The peripherals and options that can be incorporated on-chip include: • A Byte-wide Host Port • Synchronous Serial Ports Freescale Semiconductor, I • General Purpose I/O Pins • Timer With External Access • ∑∆ Codec • On-chip Oscillator • Interrupt Request Pins Other peripherals will be designed for new DSP56100 Family members. MOTOROLA DSP56100 FAMILY INTRODUCTION 1 - 5 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. DSP56100 FAMILY FEATURES nc... Freescale Semiconductor, I 1- 6 DSP56100 FAMILY INTRODUCTION MOTOROLA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. SECTION 2 CPU ARCHITECTURE OVERVIEW nc... Freescale Semiconductor, I MOTOROLA CPU ARCHITECTURE OVERVIEW 2 - 1 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. SECTION CONTENTS 2.1 INTRODUCTION . 2-3 2.2 DSP56100 BLOCK DIAGRAM . 2-3 2.2.1 Data Buses . 2-3 2.2.2 Address Buses . 2-3 2.2.3 Internal Bus Switch . 2-4 2.2.4 Bit Manipulation Unit . 2-4 2.2.5 Data ALU (DALU) . 2-4 2.2.6 Address Generation Unit (AGU) . 2-4 2.2.7 X Data Memory . 2-6 2.2.8 Program Memory . 2-6 2.2.9 Bootstrap Memory . 2-6 nc... 2.2.10 Program Control Unit (PCU) and System Stack (SS) . 2-6 2.2.11 External Bus Interface . 2-7 Freescale Semiconductor, I 2 - 2 CPU ARCHITECTURE OVERVIEW MOTOROLA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. INTRODUCTION 2.1 INTRODUCTION The heart of the DSP56100 architecture is a 16-bit multiple-bus processor designed spe- cifically for real-time digital signal processing (DSP). The overall architecture is presented and detailed block diagrams of the Data ALU and Address ALU architecture are de- scribed. 2.2 DSP56100 BLOCK DIAGRAM The major components of the CPU are: • Data Buses • Address Buses • Data ALU • Address ALU nc... • Program Control and System Stack An overall block diagram of the CPU architecture is shown in Figure 2-1. 2.2.1 Data Buses Data movement on the chip occurs over three bidirectional 16-bit buses: the X Data Bus (XDB), the Program Data Bus (PDB), and the Global Data Bus (GDB). Data transfer be- tween the Data ALU and the X Data Memory occurs over the XDB when one memory ac- cess is performed, over the XDB and the GDB when two simultaneous memory reads are performed. All other data transfers occur over the GDB. Instruction word pre-fetches take place in parallel over the PDB. The bus structure supports general register to register, reg- ister to memory, memory to register, and memory to memory data movement and can transfer up to three 16-bit words in the same instruction cycle. Transfers between buses are accomplished through the Internal Bus Switch. As a general rule, when reading any 8-bit register, the unused bits in the most significant byte are zero filled and any unused or reserved bits are read as zero. Freescale Semiconductor, I 2.2.2 Address Buses Addresses are specified for internal X Data Memory on two unidirectional 16-bit buses, X Address Bus One (XAB1) and X Address Bus Two (XAB2). Program memory addresses are specified on the bidirectional Program Address Bus (PAB). When external memory spaces have to be addressed, a single 16-bit unidirectional ad- dress bus driven by a three input multiplexer can select: XAB1, XAB2, or the PAB. One instruction cycle is needed for each external memory access. There is no speed penalty if only one external memory space is accessed in an instruction and if no wait states are MOTOROLA CPU ARCHITECTURE OVERVIEW 2 - 3 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. DSP56100 BLOCK DIAGRAM inserted in the external bus cycle. If two or three external memory spaces are accessed in a single instruction, there will be a one or two instruction cycle execution delay, respec- tively, or more if wait states are inserted on the external bus. A bus arbitrator controls ex- ternal accesses, making it transparent to the user. 2.2.3 Internal Bus Switch Transfers between buses are accomplished in the Internal Bus Switch. The internal bus switch is similar to a switch matrix and can connect any two internal buses without adding any pipeline delays. 2.2.4 Bit Manipulation Unit The bit manipulation unit performs bit manipulation and bit field manipulation on memory nc..