A Thesis entitled A BIST Architecture for Testing LUTs in a Virtex-4 FPGA by Priyanka Gadde Submitted to the Graduate Faculty as partial fulfillment of the requirements for the Master of Science Degree in Electrical Engineering _______________________________________ Dr. Mohammad Niamat, Committee Chair _______________________________________ Dr. Mansoor Alam, Committee Member _______________________________________ Dr. Weiqing Sun, Committee Member _______________________________________ Dr. Patricia R. Komuniecki, Dean College of Graduate Studies The University of Toledo December 2013 Copyright 2013, Priyanka Gadde This document is copyrighted material. Under copyright law, no parts of this document may be reproduced without the expressed permission of the author. An Abstract of A BIST Architecture for Testing LUTs in a Virtex-4 FPGA by Priyanka Gadde Submitted to the Graduate Faculty as partial fulfillment of the requirements for the Master of Science Degree in Electrical Engineering The University of Toledo December 2013 Field Programmable Gate Arrays (FPGAs) are programmable logic devices that can be used to implement a given digital design. Built-In Self-Test (BIST) is a testing technique that enables the device to test itself without the need for any external test equipment. The re-programmability feature of the FPGAs makes BIST a favorable approach for testing FPGAs because it eliminates any area or performance degradation associated with BIST. In order to ensure proper operation of Look up Tables in Xilinx Virtex-4 Field- Programmable Gate Arrays (FPGAs), a dependable and resource efficient test technique is needed so that the functional operation of the memory can be tested. Traditional BIST techniques for FPGAs suffer from a large number of logic resource requirements and long test times in the implementation and testing of the circuit. The work presented in this research simplifies the BIST architecture and reduces the test time required to test the Look up Tables in a Virtex-4 FPGA. The proposed iii technique is capable of testing the following types of memory faults: stuck-at fault, transition fault, address decoder fault, incorrect read fault, read destructive fault, deceptive read destructive fault, data retention fault, state coupling fault, transition coupling fault, incorrect read coupling fault, read destructive coupling fault, and deceptive read destructive coupling fault in a SRAM based FPGA. iv This Thesis is dedicated to my Grandparents, for all their Love and Support. Acknowledgements I would like to thank Dr. Mohammed Niamat for giving me an opportunity to work under his leadership and guiding me with his valuable advice. I would also like to thank Dr. Mansoor Alam and Dr. Weiqing Sun for serving in my thesis committee. I would also like to thank the Department of Electrical Engineering and Computer Sciences, for partially funding my Master’s degree I would like to thank my grandparents Mr. Adinarayana and Mrs. Jayasri and my parents, Mr. Ramprasad and Mrs. Karuna for their constant love, support, understanding, encouragement and for always being my source of motivation. I am very grateful to them for their sacrifices and efforts that made this thesis possible. I would love to thank my sister Hema Prasanthi for being there to share my happiness, cheer me up in tough times and being my best friend always. My acknowledgments would be incomplete without thanking my friends. Primarily, I would like to thank Pradyuma Thayi for being my best companion to help and guide me throughout my Masters. I would like to thank my friends Aditya, Ahmad, Anu, Jayaram, Karthik, Prem, Sandeep, Swetha, and Teja for all their encouragement at every step and I would like to thank my Uncle Madhusudan and Aunt Padmaja for all their love and support. vi Contents Abstract ............................................................................................................................. iii Acknowledgements .......................................................................................................... vi Table of Contents ............................................................................................................ vii List of Tables .................................................................................................................. xii List of Figures ............................................................................................................... xiii 1 Introduction ........................................................................................................... 1 1.1 Field Programmable Gate Arrays .................................................................... 1 1.2 Built in Self-Test (BIST) ................................................................................. 2 1.3 Advantages of BIST ......................................................................................... 3 1.4 Disadvantages of BIST .................................................................................... 4 1.5 Literature Survey .............................................................................................. 5 1.6 Organization of Thesis ..................................................................................... 8 2 Fault Types and Algorithms ................................................................................ 9 2.1 Introduction ...................................................................................................... 9 2.2 SRAM Cell ..................................................................................................... 11 2.3 Functional Model ........................................................................................... 11 2.4 Electrical Structure for SRAMs ..................................................................... 12 vii 2.5 SRAM Read and Write Circuitries................................................................. 14 2.6 Faults .............................................................................................................. 15 2.6.1 SRAM Memory Faults .................................................................... 16 2.7 Analysis of Faults in SRAM Cell ................................................................... 29 2.8 Advanced Memory Test ................................................................................. 32 2.9 MATS and MATS+ Algorithms .................................................................... 32 2.10 MARCH C-Algorithm.................................................................................. 33 2.11 Extended MarchC- Algorithm ...................................................................... 33 2.12 March Tests .................................................................................................. 34 2.13 Selection of the Testing Algorithm .............................................................. 35 3 SRAM Based FPGA ............................................................................................ 36 3.1 Introduction .................................................................................................... 36 3.2 Anatomy of the FPGA.................................................................................... 36 3.3 Benefits and Drawbacks of FPGAs ................................................................ 37 3.4 FPGA Applications ........................................................................................ 38 3.5 FPGA Device Manufactures .......................................................................... 39 3.6 SRAM Programmable Virtex-4 FPGA .......................................................... 39 3.6.1 I/O Blocks ....................................................................................... 40 3.6.2 Block RAM Modules (BRAMs) ..................................................... 40 3.6.3 Cascadable Embedded Xtreme DSPSlices ...................................... 41 viii 3.6.4 Digital Clock Managers (DCMs) .................................................... 41 3.6.5 Configurable Logic Block (CLBs) .................................................. 41 3.7 Need for Testing FPGAs ................................................................................ 49 4 Proposed Architecture for Testing Look up Tables in a Virtex-4 FPGA ...... 50 4.1 Test Pattern Generator (TPG) ........................................................................ 53 4.2 Circuit Under Test (CUT) and Output Response Analyzer (ORA) ............... 57 4.3 BISTArchitecture ........................................................................................... 59 4.4 Fault Modeling and Detection using Extended MarchC- Algorithm............. 62 4.5 Pseudo Code ................................................................................................... 63 4.6 Fault Modeling and Detection ........................................................................ 64 4.6.1 Stuck-at Fault .................................................................................. 64 4.6.2 Transition Fault ............................................................................... 65 4.6.3 Address Decoder Fault .................................................................... 67 4.6.4 Incorrect Read Fault ........................................................................ 69 4.6.5 Read Destructive Fault .................................................................... 70 4.6.6 Deceptive Read Destructive Fault ..................................................