Cover 88ALP01 PCI to NAND, SD and Camera Host Controller Datasheet Doc. No. MV-S103921-00, Rev. – July 17, 2007 Marvell. Moving Forward Faster Document Classification: Proprietary Information 88ALP01 Datasheet Document Conventions Note: Provides related information or information of special importance. Caution: Indicates potential damage to hardware or software, or loss of data. Warning: Indicates a risk of personal injury. Document Status Doc Status: Preliminary Technical Publication: x.xx For more information, visit our website at: www.marvell.com Disclaimer No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the express written permission of Marvell. Marvell retains the right to make changes to this document at any time, without notice. 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No. MV-S103921-00 Rev. – Copyright © 2007 Marvell Page 2 Document Classification: Proprietary Information July 17, 2007, Preliminary 88ALP01 PCI to NAND, SD and Camera Host Controller Datasheet PRODUCT OVERVIEW Overview – SD/SDIO controller The Marvell® single-chip 88ALP01 triple function device – Standard camera interface controller integrates a NAND flash controller (with Reed-Solomon Each function operating independently: ECC), an SD/SDIO controller, and a CMOS Camera – Dedicated driver Module Interface Controller (CCIC). The device is ideally – Separated configuration registers suited for laptop computing devices and other embedded – Separated buffers applications. – Separated controls The 88ALP01 package is optimized for 32-bit PCI All functions have host interrupt capability clients. The small 128-pin TQFP package with low pin Interrupts OR together and sent to INTAn count minimizes board space, simplifies signal routing, On-chip generated power-on reset and reduces the number of required PCB layers, NAND Flash controller supports both DMA and PIO resulting in cost-effective motherboard and low profile modes system implementations. SD controller supports DMA and PIO modes The 88ALP01 is optimized for maximum throughput and Camera interface controller supports DMA data low PCI Bus and CPU utilization. Adequate on-chip transfer memory buffers enable efficient PCI bus cycles and data buffering and eliminates the need for external memory. NAND Controller Direct Memory Address (DMA)-based burst data transfer Configurable to interface with different 8-bit NAND reduces CPU and PCI bus utilization and improves Flash devices (Samsung and Toshiba) overall system performance. Supports either 512 byte or 2 KB page sizes Configurable to work with different single chip NAND General Features Flash sizes from 128 Mbit to 64 Gbit Basic NAND Flash functions: PCI Interface – Page program/read Fully compliant with PCI v2.3, 32-bit, 33 MHz – Block erase – Random program/read – ID read 66 MHz support is pending final analysis of – Status read PCI timing. – Reset and lock Note Supports hardware ECC (Reed-Solomon algorithm) – 4 bit-symbol detection and correction Programmable cache line size 3.3V signalling – 12-bit per symbol with data automatic packing PCI Bus master Burst transfer SD/SDIO Supports DMA and PIO operations Supports 1-bit/4-bit SD, SDIO cards Supports PCI power states Up to 48 MHz for SD Supports three functions in a chip: Supports interrupts for information exchange between – NAND Flash Controller host and cards Copyright © 2007 Marvell Doc. No. MV-S103921-00 Rev. – July 17, 2007, Preliminary Document Classification: Proprietary Information Page 3 88ALP01 Datasheet Supports read wait commands in SD cards Camera Interface Hardware Cyclic Redundancy Check (CRC) Supports high-resolution CMOS camera module generating and checking Supports both RGB and YUV formats Supports DMA and PIO operations Standard 8-wire camera interfaces Suspend and resume in SDIO cards DMA pixel data transfer Host interrupt capability Supports programmable pixel clock Only SDMEM card has been tested at this Package time. Note 14mm x 14mm, 128 TQFP (EPAD) Lead-free package available Doc. No. MV-S103921-00 Rev. – Copyright © 2007 Marvell Page 4 Document Classification: Proprietary Information July 17, 2007, Preliminary Table of Contents Table of Contents Product Overview .......................................................................................................................................3 1 Signal Description .......................................................................................................................21 1.1 Signal Diagram................................................................................................................................................21 1.2 128-Pin TQFP Package ..................................................................................................................................22 1.3 Pin Description ................................................................................................................................................23 2 Functional Description................................................................................................................29 2.1 System Overview ............................................................................................................................................29 2.1.1 System Component Description .......................................................................................................29 2.1.1.1 Power Supplies ..................................................................................................................29 2.1.1.2 External Reference Clock...................................................................................................30 2.1.1.3 External TWSI EEPROM (VPD).........................................................................................30 2.2 Functional Overview........................................................................................................................................30 2.2.1 PCI Bus Interface Unit ......................................................................................................................30 2.2.1.1 Slave Access to Configuration Space ................................................................................31 2.2.1.2 Slave Access to Memory Resources..................................................................................31 2.2.1.3 Master Access....................................................................................................................31 2.2.1.4 Parity Generation/Check ....................................................................................................32 2.2.2 NAND Flash Controller .....................................................................................................................33 2.2.2.1 Write Operations ................................................................................................................33 2.2.2.2 Read Operations ................................................................................................................33 2.2.3 SDIO