EE382V-ICS: System-on-Chip (SoC) Lecture 8 Design EE382V-ICS: System-on-a-Chip (SoC) Design Lecture 8 - System Design Methodology with sources from: Christian Haubelt, Univ. of Erlangen-Nuremberg Andreas Gerstlauer Electrical and Computer Engineering University of Texas at Austin [email protected] SoC Design Flow Start Analyze results MRD Functionality No Met? No PRD Modify Yes Product Model? Yes Map, Model & Validation Simulate in SPW or Matlab or C System No Loop or C++ BOM Costs Met? Yes Mapping to No Platform or Components Power No Complete? Req. Met? Design Yes Yes Convergence and Analyze results Verification Schedule No Loop Req. Met? No Metrics Met? Yes Yes Platform Freeze No Req. Met? Architecture Yes No MRD Met? Return Yes EE382V-ICS: SoC Design, Lecture 8Done © 2010 A. Gerstlauer 2 © 2010 A. Gerstlauer 1 EE382V-ICS: System-on-Chip (SoC) Lecture 8 Design Design Convergence FrontFront EndEnd DesignDesign ImplementationImplementation Reduced convergence time due to minimal data Convergence time increases due to more design data Reduced convergence time due to reduced solution space Convergence time increases due to transition phase Reduced convergence time due to reduced solution space Design Converges # Optimization Solutions # Optimization # Optimization Solutions # Optimization Rapid Exploration Rapid Traversal EE382V-ICS: SoC Design, Lecture 8 © 2010 A. Gerstlauer 3 Design Challenges • Complexity • High degree of parallelism at Applications various levels • Heterogeneity Programming • Of components Model? • Of tools • Low-level communication mechanisms • Programming model Source: C. Haubelt, Univ. of Erlangen-Nuremberg EE382V-ICS: SoC Design, Lecture 8 © 2010 A. Gerstlauer 4 © 2010 A. Gerstlauer 2 EE382V-ICS: System-on-Chip (SoC) Lecture 8 Design Complexity Forces Functionality Cost Compatibility Capacity Security Availability Reliability Performance Throughput Technology churn Robustness “The challenge over the next 20 years will not be speed or cost or performance; it will be a question of complexity.” Bill Raduchel, Chief Strategy Officer, Sun Microsystems EE382V-ICS: SoC Design, Lecture 8 © 2010 A. Gerstlauer 5 Multi-Processor System-on-Chip (MPSoC) System Memory Micro- ASIP Local RAM Memory Controller Controller Controller Bus Hardware DSP DSP RAM Accelerator Bridge DSP Bus Shared Hardware Video RAM Accelerator Front End Local Bus Source: C. Haubelt, Univ. of Erlangen-Nuremberg EE382V-ICS: SoC Design, Lecture 8 © 2010 A. Gerstlauer 6 © 2010 A. Gerstlauer 3 EE382V-ICS: System-on-Chip (SoC) Lecture 8 Design MPSoC Terminology • Multi-processor • Heterogeneous, asymmetric multi-processing (AMP) • Distributed memory and operating system • Multi-core • Homogeneous, symmetric multi-processing (SMP) • Shared memory and operating system Multi-core processors in a multi-processor system • Many-core • > 10 cores per processor… EE382V-ICS: SoC Design, Lecture 8 © 2010 A. Gerstlauer 7 Processor Implementation Options Source: T. Noll, RWTH Aachen, via R. Leupers, “From ASIP to MPSoC”, Computer Engineering Colloquium, TU Delft, 2006 EE382V-ICS: SoC Design, Lecture 8 © 2010 A. Gerstlauer 8 © 2010 A. Gerstlauer 4 EE382V-ICS: System-on-Chip (SoC) Lecture 8 Design Lecture 8: Outline Introduction • System design methodology • Electronic system-level design (ESL/SLD) • ESL design • Modeling •Synthesis • Verification • ESL landscape • Summary and conclusions EE382V-ICS: SoC Design, Lecture 8 © 2010 A. Gerstlauer 9 System Design System-level design Hardware Software development development Integration & Verification EE382V-ICS: SoC Design, Lecture 8 © 2010 A. Gerstlauer 10 © 2010 A. Gerstlauer 5 EE382V-ICS: System-on-Chip (SoC) Lecture 8 Design Classical System Design Flow System requirement specification system design System architecture design Modeling Hardware design hardware softwareSoftware development development development integrationIntegration & Verification & verificationSystem manual (semi)automatic EE382V-ICS: SoC Design, Lecture 8 © 2010 A. Gerstlauer 11 Hardware-Centric Design Cycle Task Specification Fixes in specification HW design Fixes in hardware HW verification SW design Fixes in software SW verification Integration & verification Time EE382V-ICS: SoC Design, Lecture 8 © 2010 A. Gerstlauer 12 © 2010 A. Gerstlauer 6 EE382V-ICS: System-on-Chip (SoC) Lecture 8 Design Hardware-Centric Design Cycle but you want to know here … and here Task … and here Specification Fixes in specification ✘ HW design Fixes in hardware ✘ HW verification SW design Fixes in software ✘ SW verification Integration & verification ✘ Time known if project is successful EE382V-ICS: SoC Design, Lecture 8 © 2010 A. Gerstlauer 13 Electronic System-Level (ESL) Design Flow System requirement specification system design High-level model System-level design Hardware design Software development hardware software development development integrationIntegration & Verification & verificationSystem implementation manual (semi)automatic EE382V-ICS: SoC Design, Lecture 8 © 2010 A. Gerstlauer 14 © 2010 A. Gerstlauer 7 EE382V-ICS: System-on-Chip (SoC) Lecture 8 Design New ESL Design Cycle Task Specification (high-level & arch. models) Fixes in specification HW design Fixes in hardware HW verification SW design Fixes in software SW verification Integration & verification Time Find good design options here EE382V-ICS: SoC Design, Lecture 8 © 2010 A. Gerstlauer 15 Double Roof Model Software Hardware system Specification task component instruction architecture logic ISA RTL Arch Implementation gate Source: A. Gerstlauer, C. Haubelt, A. Pimentel, et al., “Electronic System-Level Synthesis Methodologies,“ TCAD, 2009. EE382V-ICS: SoC Design, Lecture 8 © 2010 A. Gerstlauer 16 © 2010 A. Gerstlauer 8 EE382V-ICS: System-on-Chip (SoC) Lecture 8 Design Design Methodologies Set of models and design steps (transformations) • Top down design • Platform based design • Starts with functional system • Starts with architecting a specification processing platform for a given – Application behavior vertical application space – Models of Computation (MoC) – Semiconductor, ASSP vendors • Successive refinement • Enables rapid creation and • Connect the hardware and verification of sophisticated SoC software design teams earlier in designs variants the design cycle. • PBD uses predictable and pre- • Allows hardware and software to verified firm and hard blocks be developed concurrently • PBD reduces overall time-to- • Goes through architectural market mapping – Shorten verification time • The hardware and software parts • Provides higher productivity are either manually coded or through design reuse obtained by refinement from • PBD allows derivative designs higher model with added functionality • Ends with HW-SW co-verification • Allows the user to focus on the and System Integration part that differentiate his design Source: Coware, Inc., 2005 EE382V-ICS: SoC Design, Lecture 8 © 2010 A. Gerstlauer 17 Top-Down ESL Design Environment Primarily Primarily Virtual PROTOTYPING ENVIRONMENT Physical HW HW DESIGN FAB INTEG. System Function SL & TEST Def. Design Design SW SW HW & SW DESIGN CODING CODESIGN Cost Models Copyright © 1995-1999 SCRA Used with Permission EE382V-ICS: SoC Design, Lecture 8 © 2010 A. Gerstlauer 18 © 2010 A. Gerstlauer 9 EE382V-ICS: System-on-Chip (SoC) Lecture 8 Design Platform-Based Design (PBD) Performance models: Models of Emb. SW, Comm. Computation and Comp. resources System System Behavior Platform Model Checking HW/SW Partitioning, Behavior Scheduling & Estimation Mapping Verification Performance Architecture Analysis and Simulation Refinement Synthesis Flow To Implementation & Coding Source: UC Berkeley, EECS249 EE382V-ICS: SoC Design, Lecture 8 © 2010 A. Gerstlauer 19 System Design Languages • Netlists • Structure only: components and connectivity Gate-level [EDIF], system-level [SPIRIT/XML] • Hardware description languages (HDLs) • Event-driven behavior: signals/wires, clocks • Register-transfer level (RTL): boolean logic Discrete event [VHDL, Verilog] • System-level design languages (SLDLs) • Software behavior: sequential functionality/programs C-based [SpecC, SystemC, SystemVerilog] EE382V-ICS: SoC Design, Lecture 8 © 2010 A. Gerstlauer 20 © 2010 A. Gerstlauer 10 EE382V-ICS: System-on-Chip (SoC) Lecture 8 Design Lecture 8: Outline Introduction System design flow • ESL design • Modeling •Synthesis • Verification • ESL landscape • Summary and conclusions EE382V-ICS: SoC Design, Lecture 8 © 2010 A. Gerstlauer 21 System Modeling • Design models as abstraction of a design instance • Representation for validation and analysis • Specification for further implementation Documentation & specification Systematic modeling flow and methodology • Set of models • Set of design steps From specification to implementation Well-defined, rigorous system-level semantics • Unambiguous, explicit abstractions, models – Objects and composition rules Synthesis and verification EE382V-ICS: SoC Design, Lecture 8 © 2010 A. Gerstlauer 22 © 2010 A. Gerstlauer 11 EE382V-ICS: System-on-Chip (SoC) Lecture 8 Design Modeling Guidelines • A model should capture exactly the aspects required by the system, and no more. • There is not one model/algorithm/tool that fits all. • Being formal is a prerequisite for algorithmic analysis. • Formality means having a mathematical definition (semantics) for the properties of interest. • Being compositional is a prerequisite for scalability. • Compositionality is the ability of breaking a task about A||B into two subtasks about A and