1 Proceedings of the 30th International Symposium on Power Semiconductor Devices & ICs May 13-17, 2018, Chicago, USA View metadata, citation and similar papers at core.ac.uk brought to you by CORE Monolithic Integration of GaN-Based NMOSprovided by Infoscience - ÉcoleDigital polytechnique fédérale de Lausanne Logic Gate Circuits with E-Mode Power GaN MOSHEMTs Minghua Zhu and Elison Matioli Power and Wide-band-gap Electronics Research Laboratory (POWERLAB) École Polytechnique Fédérale de Lausanne (EPFL) Lausanne, Switzerland [email protected], [email protected] Abstract— In this work, we demonstrate high-performance NOT NAND NOR NMOS GaN-based logic gates including NOT, NAND, and NOR 5 by integration of E/D-mode GaN MOSHEMTs on silicon ()WL/ 4 α = E ()WL/ substrates. The load-to-driver resistance ratio was optimized in Vout Vout Vout D (V) 3 these logic gates by using a multi-finger gate design of E-mode α =1 out α GaN MOSHEMT to increase the logic swing voltage and noise V 2 =2 α α=4 margins, and reduce the transition periods. State-of-the-art Vin VA VA VB 1 α=10 NMOS inverter was achieved with logic swing voltage of 4.93 V V at a supply voltage of 5 V, low-input noise margin of 2.13 V and B 0 (a) (c) 012345 high-input noise margin of 2.2 V at room temperature. Excellent E-mode Vin (V) high temperature performance, at 300°C, was observed with a D-mode GND Vin Vout VDD logic swing of 4.85 V, low-input noise margin of 1.85 V and high- Vin NOT output noise margin of 2.2V. In addition, GaN-based NAND and D-mode NOR NMOS logic gates are reported for the first time with very good performance. Finally, the logic gates were monolithically GND VDD integrated with high-voltage E-mode power transistors, which AlGaN reveals a significant step forward towards monolithic integration GaN of GaN power transistors with gate drivers. Si substrate E-mode Vout Keywords— Logic gates, GaN, high temperature, inverters, (b) (d) NAND, NOR, E-mode, D-mode, monolithic integration Fig. 1. (a) Equivalent circuits of inverter, NAND and NOR logic gates. (b) Cross-sectional schematic and (c) top view of monolithic integration of E/D- mode MOSHEMTs. (d) Simulated transfer characteristics versus different α I. INTRODUCTION ratios. The high switching frequency of GaN-based power GaN devices [4], [5]. Ideas to demonstrate purely n-type logic converters can lead to a significant reduction of the size of circuits date back of more than 30 years with NMOS logics passive components, such as capacitors and inductors, and [6]–[8], also named direct-coupled FET logic (DCFL). GaN thus, increasing the power density of the overall system [1], DCFLs have been demonstrated [9]–[12], however their [2]. GaN is one of the most promising materials for high performances are not sufficient to satisfy the logic frequency power switching due to its exceptional properties requirements, due to their small noise margins, large logic such as large saturation velocity, high carrier mobility, and transition voltages, small logic swing and large low-level high breakdown field strength. Despite the advantages of GaN output voltages (VOL). Recent research show steady power devices, discrete Si-based logic control and gate drivers improvements on GaN DCFL [10], however the VOL is still are still used to control the GaN power devices [3], which quite high, up to 0.3 V and the maximum voltage swing is 4.66 limits the switching frequency due to parasitic inductances V, which would lead to high logic losses and safety problems. from external connections of GaN power devices and gate A very distinct property of GaN compared to Silicon is its high drivers. temperature operation, which led to the demonstration of GaN DCFLs operating at high temperatures, up to 375 °C [9], [11], A monolithic integration of GaN power devices with GaN- however, it resulted in a much degraded operation compared to based gate drivers would minimize parasitic components and room temperature (RT). unveil the full potential of GaN transistors for high frequency power conversion with high efficiency. GaN-based logic gates In this paper, we demonstrate high-performance NOT, are essential components to realize level shift, driver control, NAND and NOR logic gate units by integrating E/D-mode dead time control and under voltage-lockout (UVLO) for driver MOSHEMTs. These logic units were optimized for larger circuits. However, high performance CMOS logics in GaN are voltage swing, wider noise margin, and smaller transition not feasible today due to the poor transport properties of p-type This work was supported in part by the Technology Research Programme (TRP) of the European Space Agency. ©2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. 2 periods. High performance was observed even up to 300°C, which could be applied for high temperature applications. II. INTEGRATED LOGIC DESIGN AND FABRICATION The NMOS logic gate circuits, shown in Fig. 1(a), were fabricated on AlGaN/GaN epitaxial layer on silicon substrate (Fig. 1(b)) consisting of 3.75 μm buffer, 322 nm of un-doped GaN channel, 23.7 nm of AlGaN barrier and 2.4 nm of GaN cap layer. D-mode and E-mode MOSHEMTs were fabricated at the same time, with the sole difference of one additional gate recess process to achieve E-mode operation. To optimize the design of the logics, we simulated the driver-to-load α = ()()WL// WL Fig. 2. Surface morphology (a) before and (b) after TMAH treatment. resistance ratio ED , as shown in Fig. 1 (c), where W and L are the width and length of the E- and D-mode 5 300 transistors respectively. Larger values of α result in sharper e-mode transitions, higher logic voltage swings and higher noise 4 transitor α margins, since the equivalent resistance of E-mode transistor 200 3 is much smaller than the overall resistance of the circuit. To (V) achieve large values of α, we designed a multi-finger structure out α V 2 = 1 for the E-mode MOSHEMT that results in a much smaller α 100 (mA/mm) = 4 d resistance of the E-mode compared to the D-mode device 1 α = 16 I without oversizing too much the E-mode transistor (Fig. 1(d)). α = 32 The chip fabrication started with the definition of the mesa 0 0 012345 regions by Cl2-based inductively coupled plasma (ICP) (a) Vin (V) etching. For the E-mode devices, a 1.5 μm-long gate recess 5 was defined by optical lithography and followed by a Cl2- 0.04 Ratio RE/RD based slow-rate dry etching, which leads to a precise control 4 0.02 of the etching depth. To improve the surface morphology after 0 gate recess, therefore the electron transport of the e-mode 3 100 200 300 devices, we have combined a slow, low-damage ICP etch with (V) T (°C) o out a 5%-TMAH wet treatment performed at 80 C for 30 minutes V 2 RT (Fig. 2). This step is very critical to obtain a good threshold 100°C voltage (Vth) control and reasonable on-resistance (Rdson) of E- 1 200°C mode transistor. A metal stack of Ti (200 )/Al (1200 )/Ti 300°C 0 (400 )/ Ni (600 )/ Au (500 ) was deposited in the source 012345 (b) and drain contact regions by electron-beam evaporation, Vin (V) followed by rapid thermal annealing at 830°C under N2 Fig. 3. (a) DCFL VTC versus different α ratio and the transfer characteristics atmosphere. The gate dielectric was 25 nm-thick SiO2 of E-mode transistors (b) DCFL VTC under different temperature varied deposited by atomic layer deposition (ALD) at 300°C, from RT to 300°C. Inset: resistance ratio of E/D-mode logic versus temperature for output logic equal to 0. immediately after a surface treatment in 37% HCl for 1 min. resistance of the E- and D-mode transistors increases at the Finally, gate and contact pads were formed by depositing Ni/Au for both E-mode and D-mode devices. Fig. 1(d) shows same rate with temperature (inset of Fig. 3(b)), which results the integration of these devices for the NOT logic gate. in a nearly constant E/D-mode resistance ratio and thus in a similar VOL since: III. RESULTS AND DISCUSSION R VV= E (1) OL RR+ DD A. DCFL inverter ED Fig. 3(a) shows the measured voltage transfer As shown in Fig. 3(a), the transition voltage of the DCFL characteristics (VTC) for DCFL inverters with different α, inverter is affected by two main factors: the Vth of the E-mode which is consistent with the simulations shown in Fig. 1(c). transistor and the ratio α. For high performance logics, the The performance of the DCFL inverters was characterized ratio α must be as large as possible and the Vth of E-mode with a VDD of 5 V from RT to 300 °C revealing a proper transistor must be close to VDD/2 = 2.5 V in linear scale, which operation with very little variations for this entire temperature can be controlled by adjusting the gate recess depth. range (Fig. 3(b)). The VOL was nearly unchanged, since the 3 5 5 5 VA=0 VA=1 VOH=5V NML=2.13V 4 VA VB Vout 4 4 001 T=25°C 3 3 (V) (V) 011 out 3 VTR out 2 2 101 V (V) V out 1 110 1 V 2 VOL VIL VIH 0 (a) (b) VOL 0 1 5 5 NMH=2.2V VA=VB VA= VB VOL=0.07V 4 VA VB Vout 4 0 001 012345 3 3 (V) (a) V (V) 011 (V) in VIL VIH out 5 out 2 2 V V 101 VOH=5V NML=1.85V 110 4 1 1 (c) VOL (d) T=300°C 0 0 V 0123450 12345 3 TR V (V) V (V) (V) B B Fig.