EE247 Lecture 10 • Switched-capacitor filters (continued) – Switched-capacitor integrators • DDI & LDI integrators – Effect of parasitic capacitance – Bottom-plate integrator topology – Switched-capacitor resonators – Bandpass filters – Lowpass filters – Switched-capacitor filter design considerations • Termination implementation • Transmission zero implementation • Limitations imposed by non-idealities EECS 247 Lecture 10 Switched-Capacitor Filters © 2008 H. K. Page 1 Switched-Capacitor Integrator C φ φ I φ 1 2 1 Vin - φ 2 Cs Vo + T=1/fs C C φ I φ I 1 2 Vin Vin - - C C s s Vo Vo + + φ High φ 1 2 High Æ C Charged to Vin s ÆCharge transferred from Cs to CI EECS 247 Lecture 10 Switched-Capacitor Filters © 2008 H. K. Page 2 Switched-Capacitor Integrator Output Sampled on φ1 φ φ 1 2 Vin CI φ - 1 Cs Vo Vo1 + φ φ φ φ φ Clock 1 2 1 2 1 Vin VCs Vo Vo1 EECS 247 Lecture 10 Switched-Capacitor Filters © 2008 H. K. Page 3 Switched-Capacitor Integrator ( (n-1)T n-3/2)Ts s (n-1/2)Ts nTs (n+1/2)Ts (n+1)Ts φ φ φ φ φ Clock 1 2 1 2 1 Vin Vs Vo Vo1 Φ 1 Æ Qs [(n-1)Ts]= Cs Vi [(n-1)Ts] , QI [(n-1)Ts] = QI [(n-3/2)Ts] Φ 2 Æ Qs [(n-1/2) Ts] = 0 , QI [(n-1/2) Ts] = QI [(n-1) Ts] + Qs [(n-1) Ts] Φ 1 _Æ Qs [nTs ] = Cs Vi [nTs ] , QI [nTs ] = QI[(n-1) Ts ] + Qs [(n-1) Ts] Since Vo1= - QI /CI & Vi = Qs / Cs Æ CI Vo1(nTs) = CI Vo1 [(n-1) Ts ] -Cs Vi [(n-1) Ts ] EECS 247 Lecture 10 Switched-Capacitor Filters © 2008 H. K. Page 4 Switched-Capacitor Integrator φ Output Sampled on 1 φ φ 1 2 Vin CI φ - 1 Cs Vo Vo1 + =−⎡ −−⎤⎡⎤ CV(nT)CVIIos o⎣(n 1)Ts ⎦⎣⎦ CV sin (n 1)Ts C V(nT)Voso=−⎡⎤(n−− 1)Tsss V ⎡⎤ (n 1)T ⎣⎦CI in ⎣⎦ −−11C Voo (Z)=− Z V (Z) Zs V (Z) CI in − Vo =−Cs × Z 1 (Z) − CI 1−Z 1 Vin DDI (Direct-Transform Discrete Integrator) EECS 247 Lecture 10 Switched-Capacitor Filters © 2008 H. K. Page 5 Switched-Capacitor Direct-Transform Discrete Integrator C φ φ I 1 2 Vin φ - 1 Cs Vo + − Vo =−Cs × z 1 (z) − CI 1−z 1 Vin C =−s × −1 C1I z EECS 247 Lecture 10 Switched-Capacitor Filters © 2008 H. K. Page 6 DDI Switched-Capacitor Integrator C φ φ I 1 2 Vin φ - 1 Cs Vo + − Vo =−Cs ×z 1 = jTω (z)− , z e CI 1−z 1 Vin αα− − jT/2ω jj− =×CCss1 = ×e α =ee ωωω− since: sin CCII1−−eeejT jT/2 jT/2 2j − ω =−jeCs ×jT/2 × 1 CI 2sin()ωT/2 Cs 1 ωT/2 − jT/2ω =−ω × × e CjTI sin()ωT/2 ror se Er Ideal Integrator Magnitude Error Pha EECS 247 Lecture 10 Switched-Capacitor Filters © 2008 H. K. Page 7 DDI Switched-Capacitor Integrator C φ φ I 1 2 Vin φ - 1 Cs Vo + Example: Mag. & phase error for: 1- f / fs=1/12 Æ Mag. error = 1% or 0.1dB Phase error=15 degree Qintg = -3.8 2- f / fs=1/32 Æ Mag. error=0.16% or 0.014dB Phase error=5.6 degree DDI Integrator: Æ magnitude error no problem Qintg = -10.2 phase error major problem EECS 247 Lecture 10 Switched-Capacitor Filters © 2008 H. K. Page 8 5th Order Low-Pass Switched Capacitor Filter jω Built with DDI Integrators jω ω s s-plane s-plane Coarse View Fine View σ σ Example: 5th Order Elliptic Filter Ideal Pole Singularities pushed -ω Ideal Zero s towards RHP due to DDI Pole integrator excess phase DDI Zero EECS 247 Lecture 10 Switched-Capacitor Filters © 2008 H. K. Page 9 Switched Capacitor Filter Build with DDI Integrator H ()jω Passband Peaking SC DDI based Filter Zeros lost! fs /2 Frequencyf (Hz) 2f f Continuous-Time s s Prototype EECS 247 Lecture 10 Switched-Capacitor Filters © 2008 H. K. Page 10 Switched-Capacitor Integrator Output Sampled on φ2 C φ φ I 1 2 Vin φ - 2 Cs Vo Vo2 + Sample output ½ clock cycle earlier Æ Sample output on φ2 EECS 247 Lecture 10 Switched-Capacitor Filters © 2008 H. K. Page 11 Switched-Capacitor Integrator Output Sampled on φ2 (n-3/2)Ts (n-1)T s (n-1/2)Ts nTs (n+1/2)Ts (n+1)Ts φ φ φ φ φ Clock 1 2 1 2 1 Vin Vs Vo2 Φ 1 Æ Qs [(n-1)Ts]= Cs Vi [(n-1)Ts] , QI [(n-1)Ts] = QI[(n-3/2)Ts] Φ 2 Æ Qs [(n-1/2) Ts] = 0 , QI [(n-1/2) Ts] = QI [(n-3/2) Ts] + Qs [(n-1) Ts] Φ 1 _Æ Qs [nTs ] = Cs Vi [nTs ] , QI [nTs ] = QI[(n-1) Ts ] + Qs [(n-1) Ts] Φ 2 Æ Qs [(n+1/2) Ts] = 0 , QI [(n+1/2) Ts] = QI [(n-1/2) Ts] + Qs [n Ts] EECS 247 Lecture 10 Switched-Capacitor Filters © 2008 H. K. Page 12 Switched-Capacitor Integrator Output Sampled on φ2 (n-3/2)Ts (n-1)T s (n-1/2)Ts nTs (n+1)Ts φ φ φ φ φ Clock 1 2 1 2 1 Vin Vs Vo QI [(n+1/2) Ts] = QI [(n-1/2) Ts] + Qs [n Ts] Vo2= - QI /CI & Vi = Qs / Cs Æ CI Vo2 [(n+1/2) Ts] = CI Vo2 [(n-1/2) Ts ] -Cs Vi [n Ts ] Using the z operator rules: V − o2 =−Cs × z 1/2 (z) − Æ C V z1/2 = C V z-1/2 - C V CI 1−z 1 I o2 I o2 s i Vin EECS 247 Lecture 10 Switched-Capacitor Filters © 2008 H. K. Page 13 LDI Switched-Capacitor Integrator C LDI (Lossless Discrete Integrator) Æ φ φ I 1 2 same as DDI but output is sampled ½ Vin φ clock cycle earlier - 2 LDI Cs Vo2 V − + o2 =−Cs ×z 1/2 = jTω (z)− , z e CI 1z− 1 Vin − ω =−CCse ×jT/2 = s × 1 −−+ωωω CCII1−−eeej T j T/2 j T/2 =−j Cs × 1 CI 2sin()ωT/2 Cs 1 ωT/2 =−ω × No Phase Error! CjTI sin()ωT/2 For signals at frequencies << sampling freq. Æ Magnitude error negligible Ideal Integrator Magnitude Error EECS 247 Lecture 10 Switched-Capacitor Filters © 2008 H. K. Page 14 Switched-Capacitor Filter Built with LDI Integrators H ()jω Zeros Preserved Frequencyf (Hz) 2f fs /2 s s f EECS 247 Lecture 10 Switched-Capacitor Filters © 2008 H. K. Page 15 Switched-Capacitor Integrator Parasitic Capacitor Sensitivity C φ φ I 1 2 Vin - Vo Cp2 C Cs p3 + Cp1 Effect of parasitic capacitors: 1- Cp1 - driven by opamp o.k. 2- Cp2 - at opamp virtual gnd o.k. 3- Cp3 – Charges to Vin & discharges into CI Æ Problem parasitic capacitor sensitivity EECS 247 Lecture 10 Switched-Capacitor Filters © 2008 H. K. Page 16 Parasitic Insensitive Bottom-Plate Switched-Capacitor Integrator Sensitive parasitic cap. Æ Cp1 Æ rearrange circuit so that Cp1 does not charge/discharge φ 1=1 Æ Cp1 grounded φ 2=1 Æ Cp1 at virtual ground φ φ CI 1 2 - C C s p1 Vo + Vi+ Cp2 Vi- Solution: Bottom plate capacitor integrator EECS 247 Lecture 10 Switched-Capacitor Filters © 2008 H. K. Page 17 Bottom Plate Switched-Capacitor Integrator φ φ φ CI 1 1 2 Vo1 - φ Cs 2 Vo + Vo2 Vi+ Vi- Output/Input z-Transform Vo1 Vo2 Note: on φ1 on φ2 − 1 Different delay from Vi+ & −1 2 Vi+ CCsszz Vi- to either output CC−−11 on φ1 II1z−− 1z Æ Special attention needed for input/output connections Vi- −1 −−CCssz12 to ensure LDI realization on φ2 −− CCII1z−−11 1z EECS 247 Lecture 10 Switched-Capacitor Filters © 2008 H. K. Page 18 Bottom Plate Switched-Capacitor Integrator z-Transform Model φ φ CI φ 1 2 1 − −1 zz1 - 2 Vo1 −−C11φ 1z−−s 1z 2 Vo + Vo2 Vi+ −1 z12 − Input/Output−− z-transform Vi- 1z−−11 1z −1 Vi+ CCs I 2 −1 Vo1 z z 2 − −1 + 1 Vi- −CCs I 1z z 2 Vo2 LDI EECS 247 Lecture 10 Switched-Capacitor Filters © 2008 H. K. Page 19 LDI Switched-Capacitor Ladder Filter Cs − Cs CI CI + 1 +1 2 - 2 + 1 z − z z 2 1 1 1 1 1 τ τ − 1 − sτ s 4 s 5 2 − 2 3 z 2 z + - + - − z − − 1 − − 1 1z 1z− 1 1z 1 1 − − 2 2 z +1 z 2 C C z C s − s Cs − s C C C I I CI I Delay around integrator loop is (z-1/2 . z+1/2 =1) Î LDI function EECS 247 Lecture 10 Switched-Capacitor Filters © 2008 H. K. Page 20 Switched-Capacitor LDI Resonator Resonator Signal Flowgraph φ φ ω 1 2 − 1 s ω2 φ φ s 2 1 C ω ==×1 1 1sf RCeq1 2 C 2 C ω ==×1 3 2sf RCeq3 4 C 4 EECS 247 Lecture 10 Switched-Capacitor Filters © 2008 H. K. Page 21 Fully Differential Switched-Capacitor Resonator • Note: Two sets of S.C. bottom plate networks for each differential integrator φ φ 1 2 φ φ 1 2 EECS 247 Lecture 10 Switched-Capacitor Filters © 2008 H. K. Page 22 Switched-Capacitor LDI Bandpass Filter Utilizing Continuous-Time Termination Bandpass Filter Signal Flowgraphω − 0 CQ V s o1 Vo2 Vi -1/Q Vos ω0 s C C V ω =×3 =×1 o2 0sff s CC42 C Q = 2 C Q Vi EECS 247 Lecture 10 Switched-Capacitor Filters © 2008 H.