Europaisches Patentamt European Patent Office © Publication number: 0 565 914 A1 Office europeen des brevets EUROPEAN PATENT APPLICATION © Application number: 93104769.0 int ci 5 G06F 1/32 @ Date of filing: 23.03.93 © Priority: 15.04.92 US 870124 Inventor: Lee, Nathan Junsup 19 Scher Drive © Date of publication of application: New York City, New York 10956(US) 20.10.93 Bulletin 93/42 Inventor: Leontiades, Kyriakos 353 N.W. 22 Street 0 Designated Contracting States: Boca Raton, Florida 33431 (US) DE FR GB Inventor: Novak, Frank Peter 82 Oak Avenue © Applicant: International Business Machines Park Ridge, New Jersey 07656(US) Corporation Inventor: Sharma, Vikram Old Orchard Road 32 Hillview Drive Armonk, N.Y. 10504(US) Pleasantville, New York 10570(US) @ Inventor: Kannan, Krishnamurthi 2715 Evergreen Street © Representative: Monig, Anton, Dipl.-lng. Yorktown Heights, New York 10598(US) IBM Deutschland Informationssysteme Inventor: Jones, Christopher Dane GmbH, 1356 Dorchester Drive Patentwesen und Urheberrecht Georgetown, Kentucky 40324(US) D-70548 Stuttgart (DE) (sf) A system for distributed power management in portable computers. © The present invention provides a system and function of the conditions sensed by the sensing method for managing power in a portable, pen- means. based notebook computer. The system and method provides a means for minimizing power consumption by collecting and interpreting power related data at various processing elements while hiding many of the details from the end-user. The present invention is a system and method for monitoring, collecting and acting upon power-related data in a portable computer to maximize the amount of time the porta- ble computer can be used between battery re-charg- ing with minimal user intervention. The present in- vention is comprised of a plurality of independently controllable power planes which are selectively powered so that the portable computer consumes CO the minimum power necessary to perform a particu- lar function and a plurality of central processing units (CPUs) operating asynchronously with respect to each other. The present invention is further com- prised of an on/off glue logic means for monitoring battery condition, user invoked functions, and sys- tem state and a power management means for con- trolling the operation of each of the CPUs as a Rank Xerox (UK) Business Services (3. 10/3.6/3.3. 1) 1 EP 0 565 914 A1 2 Technical Field advanced processors such as the Intel 80286/386 operating in the so-called protected mode of opera- This invention relates generally to computers. tion. In these processors, the location of the inter- More specifically, this invention relates to the man- rupt vectors is not fixed. As a result, the address agement of power in portable computers. 5 lines external to the Central Processing Unit (CPU) cannot be monitored to determine if a particular Background Art interrupt is vectored to a particular location. Nor can they be relied upon to work correctly in multi- Reducing power consumption in portable com- tasking environments such OS/2 or the more recent puters has gained a great deal of attention in the io Penpoint operating system developed by GO. technical community as a result of a set of conflic- Corp. for pen-based computers. Such operating ting user requirements and technological con- systems generally do not issue software interrupts straints. On the one hand, users would like to to indicate an idle state. Furthermore, in the ad- operate these portable machines for extended vanced processors cited above, the interrupt vec- periods of time without access to ac power. This 75 tors themselves are not guaranteed to be in any means that such machines must carry their own given memory address. Thus, while the POQET power sources, i.e., batteries of various types. On design works well with real mode DOS applica- the other hand, the total energy stored in such tions, it is inadequate for environments using multi- batteries varies almost directly in proportion to their tasking operating systems executing on processors weight. Carrying heavy batteries of course, detracts 20 such as 386. from the portability attributes of these machines. U.S Pat. No. 5,041,964 to Cole et al. describes Therefore, efforts in the industry have focused the power management hardware and software of a in several related areas. First, designing compo- GRID laptop computer. In this computer, a standby nents that consume less power than corresponding mode is defined in which power to most parts of components in desktop ac-powered machines; sec- 25 the computer except dynamic memory is removed ond, detecting when such components are not in when one of a set of pre-defined events occurs. use and turning them off or placing them in a lower Power is restored to the system when the user so power consuming mode(s), thus reducing their en- indicates (by a push button) and there is sufficient ergy consumption over time; third, using batteries battery power to enable proper system functioning. that provide higher energy-to-weight ratios; and 30 As in the case of the POQET computer, the solu- last, monitoring the battery and providing the user tions in this patent break down in a multitasking alerts and related actions due to the non-linear environment where multiple applications may be nature of battery power output as a function of active at once and in advanced microprocessors time. such as the Intel 80386 and compatibles wherein The power management techniques which are 35 the operating system can (and does) disable NMI currently practiced in the personal computer in- interrupts from occurring or re-vectors them to dustry commonly address a combination of one or code fragments that may have no knowledge of the more of these areas. U.S. Pat. No. 373,440 to nature of NMI being presented to the computer. Harper et al. describes the design elements of the In the European Patent Application No. POQET computer. The POQET computer has been 40 90311832.1, Watts and Wallace describe an ap- designed with several low power components such paratus and a method whereby the CPU clock is as low power display element, low power Universal reduced whenever a real-time monitor determines Asynchronous Receive Transmit (UART) compo- that CPU activity level is low. The reduced clock nent, etc. Additionally, circuitry has been designed rate results in lower power consumption by the that detect the occurrence of certain key events in 45 CPU. Such apparatus has been incorporated in the system such as the occurrence of a key press highly integrated chip sets available from several on the keyboard, system timer signal, access to a chip vendors. However, Watts does not teach how special memory location commonly known as the to apply such techniques when multiple CPUs are interrupt vector, etc. The occurrence of any of involved in the operation of a computer. In fact, these events triggers a Non-Maskable Interrupt 50 applying the above methods to a single micropro- (NMI) to the processor which then executes a spe- cessor, albeit the main processor, without overt cial block of power management code. This code coordination among the principal points of intel- then determines if a change in the power state of ligence within the system may result in a net the system is warranted. There are several increase in power consumption. drawbacks to this approach. The scheme of moni- 55 International Pat. Appln. No. PCT/US89/05576 toring processor access to certain interrupt vector to Bolan et al., a method whereby the power con- locations and thereby deducing that the operating sumed by a certain microprocessor can be con- system and/or applications are idle, don't apply to trolled externally by a chip. This chip is designed 2 3 EP 0 565 914 A1 4 to consume very low power. As in the previous eration under low charge conditions. At the service teachings, such methods and apparatus are readily processor level, circuits are provided to monitor the available from a number of chip vendors. What is on/off button and to communicate power manage- missing from the Bolan device is a description of ment events and battery state information to the how these mechanisms can be applied to the de- 5 main processor on the system planar. The system sign of a distributed power managed computing firmware and operating system software levels ex- platform such as a pen based tablet computer. ecute on the main processor on the system planar Other implementations, including the IBM lap- and are responsible for policy decisions such as top computer (the PS/2 L40SX computer), have when power planes can be shut down and what to provided for user specifiable time-outs for various io do when a power event takes place. power consuming devices. When no input/output (I/O) activity is perceived for a time-out period on a Features and Advantages given component, that component is placed in a low power state. For example, many implementa- It is an advantage of the present invention to tions include a specifiable time out value for the is distribute the power management function among hard file. At the end of the time out period, if no three processors, thereby reducing the amount of activity has occurred, the device is turned off. processing time the main CPU is required to dedi- However, it must be noted that extra power is cate to the power management function. expended when the hard file is turned on again and It is a further advantage of the present inven- furthermore, the CPU has to wait (wasting energy) 20 tion not having to monitor address patterns to ob- while the spin-up is taking place.