TECHNICAL INFORMATION SURFACE MOUNT ZERO DEFECT DESIGN CHECK LIST by John Maxwell AVX Corporation Abstract: Reliable, high-yield SMT assemblies are easily realized if time is taken in the beginning to insure yields and reliability. You cannot slap components down on a PC board with solder and hope for manufacturability; the PC board must be designed to be manufacturable. SURFACE MOUNT ZERO DEFECT DESIGN CHECK LIST by John Maxwell AVX Corporation Introduction Surface mount technology (SMT) has suffered resistors, but can occur with SOTs (small outline transis- through several false starts, but is now a reality due to tors) or even small ICs like an SO-8 resulting in rework. circuit density needs. SMT designs are a radical depar- Inadequate solder is the source of weak or missing ture from their thru-hole counterparts due to trace/ solder joints for passive components and coplanarity component spacings, size, and sensitivity to processing. problems (opens) with ICs. There must be a proper It is mandatory that a design be manufacturable in the balance between non-coplanar parts like ICs that need very beginning as tweeks in the process and rework more solder than small chip components which require must be avoided. ZERO DEFECT SOLDERING must less solder for proper joints and low manufacturing be the goal for all SMT designs, and the path starts with defects. As a side note, the total equivalent wet laydown the design of the board. of solder paste to accommodate both passives and For a board to be manufacturable one must be able to actives should be <10–12 mils and must take the board first assemble (place) components accurately and then solder plating into account. For example, 3 mils of solder those components to the substrate (PC board) solder plate is equivalent to 5–6 mils wet laydown of with reliable solder joints, inspect those joints, test the solder paste. assembly, and finally replace any defective components. Rework, a hideous term which implies constantly fixing a production problem, must be eliminated by design FORCE DUE TO FORCE EXERTED FORCES ADHESION OF BY THE MASS DUE TO and process control. Only the design aspect will be con- SOLDER TO OF THE PART SOLDER sidered, but proper process control is as important as THE LAND SURFACE design for both high yield and reliability. TENSION Zero defect soldering requires proper solder fillet formation. Important factors that determine fillet T M T formation are slightly different between reflow and wave soldering and will be considered separately. Common design factors will be considered as a third L L category and will include tooling holes, test points, and handling stress. Figure 1. Defect and Counterdefect Forces Reflow Soldering Solder Fillet There are five major sources of induced defects for Open Solder Joint reflow soldering which fall into two categories; opens or Solder bridges (shorts). Pad design and solder mass present are Capacitor Body Land certainly the most important sources of defects but trace/pad interaction, solder mask design, and compo- nent orientation must be taken into consideration to Substrate achieve zero defects. Solder Mass. Excessive solder is the biggest source of Figure 2. A Drawbridge chip component defects; opens or drawbridges. Great globs of solder or bulbous solder joints are easy to see or Pad Design. Solder fillet shape and size is ultimately may even be required by the military, but do nothing for determined by the pad design. Unfortunately there is a strength, increase assembly post solder handling dam- profusion of recommended pads by component manu- age, and kill yields with drawbridged chip capacitors and facturers, government agencies, industry associations, resistors. Also excessive solder can cause bridging and component users to name a few; but which has between fine pitch IC leads leading to additional rework “THE PADS” is the question. Pads recommended by to fix a production problem. government agencies result in bulbous, easy-to-see Surface tension forces exerted by molten solder is the solder joints that are neither reliable nor manufac- defect generating force of coplanar parts like chip capac- turable. Excessive solder increases soldering defects itors, resistors, or transistors. It is counteracted by the (tombstoning) and makes components more sensitive to mass of the part and the moment arm created by the handling damage (cracks). Remember when you sit component length and adhesion of molten solder to the down for an IRS audit and the agent says, “I’m with the opposite end. government and I’m here to help you.” Would you Excessive solder or an imbalance of these forces believe him? result in a drawbridge or a missing solder joint. Draw- There are a few industry association pad or land pat- bridging is not a problem with just chip capacitors or tern and design guidelines that are an excellent place to start as baseline documents. The most comprehensive set of standards is available from The Institute for Interconnecting and Packaging Electronic Circuits. The guideline of most interest will be IPC-SM-782, “Surface Mount Land Patterns (Configurations and Design SOLDER Rules).” One thing to remember is that any industry MIGRATION association specification is arrived at through compromise DURING by various members who may have little SMT manufac- REFLOW turing experience. IPC-SM-782 is a prime example of this, many land patterns were established to make it easy to create artwork without understanding the impact on SOLDER LANDS yield. Just now members are doing a study to see if the and TRACES patterns are usable; a bit late because the specification is in its final form. This is still a good base line document. COMPONENT The best source for pads is either users or vendors ROTATION that have reliable, low defect solder joint histories that number in tens of millions. Certain IC and passive component vendors have this history but their pads are different from IPC-SM-782, but no compromise for ease of artwork generation was made at the expense of relia- SOLDER SOLDER CAPACITOR LAND bility or yields. Actually small components are more MIGRATION prone to soldering defects than larger parts due to their low mass and small termination surface area. Pads demand that they have some prior history, are symmetrical, and have been tested in the intended pro- cess. Always avoid “Universal Pads” because too much has been compromised. Texas Instruments and Signet- ics are good sources for IC pads with AVX and Bourns for various passive component pads. Once pads are Figure 3. Design Techniques to Avoid chosen, test them in your manufacturing process, then thermal cycle and environmentally test the assembly. Trace Pad Interaction. Connecting traces to pads is one area where thru-hole design techniques are absolutely not applicable. Reflow soldering uses heat transfer from the PC board surface to the pads, reflow- ing the solder paste on to the component termination. Asymmetry in pad thermal mass results in drawbridges or missing solder joints of low mass components or sol- der migrating away from a solder joint during reflow. Vias or plated thru-holes present another major prob- lem: capillary action of solder in the via can rob a pad of solder causing a starved or missing solder joint. A few common sense rules are in order: 1) Limit the number of traces entering a pad to a sin- gle trace if possible to reduce solder migration. 2) Symmetry is important. Balance the trace entry to a pad to minimize any induced component rotation. 3) No vias or plated thru-holes in a pad: sucks solder out of the joint. 4) Isolate ground planes from components with necked down conductors no closer than 10 mils or wider than 10 mils for passive device pads and no wider than 7 mils for active device pads. 5) Isolate a via pad even further than ground planes due to capillary action. Pad separation should be no closer than 15 mils. 0.010" Max. (.25mm) 0.010" Max. There is a simple test to see if an existing design is (.25mm) manufacturable or to find potential defect sources with a problem board. Screening solder paste on the pads with a stencil and then reflowing the board without compo- nents will indicate if there are problem locations. Solder missing from pads after reflow is a prime sign for prob- lems and allows close scrutiny of traces and pads. High 0.010" Min. 0.015" Min. yield demands that a board must have uniform solder on (.25mm) (.4mm) pads after reflow or rework will result. Remember, rework is hideous and must be avoided and is counter to reasons for adopting SMT. Figure 4. Design Techniques That Work Solder Mask Design. Again, thru-hole PC board base copper pad, exceeded 2 mils, detectable capacitor design techniques are inadequate for zero defect surface drawbridging resulted. One ounce of copper is 0.7 mils mount assemblies. Solder mask materials come in many thick and 2 ounces of copper is 1.4 mils, placing a practi- varieties ranging from dry film laminate to screened cal solder mask thickness limit of 3 mils maximum on wet film or photoimagable liquid solder mask. Solder 1-ounce copper boards and 3.5 mils for 2-ounce boards. mask thickness ranges from 0.6 mil to 9 mils across These thickness limits are in the middle of dry film mask types. Dry film ranges typically from 3-4 mils, thickness range and are much less than many wet film photoimagable from 0.6 to 6 mils across various manu- or photoimagable liquid solder masks. Elimination of facturers, but is quite tight within a single supplier (i.e., solder mask between pads removes solder mask thick- ∆s of only a mil) and wet film has the largest variation of ness problems as a defect source.