MPR601UM-01 MPC601UM/AD PowerPC™ 601 RISC Microprocessor User's Manual CONTENTS Paragraph Page Title Number Number About This Book Audience .............................................................................................................. xlii Organization......................................................................................................... xlii Additional Reading ............................................................................................. xliv Conventions ........................................................................................................ xliv Acronyms and Abbreviations ............................................................................. xliv Terminology Conventions ................................................................................. xlvii Chapter 1 Overview 1.1 PowerPC 601 Microprocessor Overview............................................................. 1-1 1.1.1 601 Features..................................................................................................... 1-2 1.1.2 Block Diagram................................................................................................. 1-3 1.1.3 Instruction Unit................................................................................................ 1-5 1.1.3.1 Instruction Queue......................................................................................... 1-5 1.1.4 Independent Execution Units........................................................................... 1-5 1.1.4.1 Branch Processing Unit (BPU).................................................................... 1-6 1.1.4.2 Integer Unit (IU) .......................................................................................... 1-6 1.1.4.3 Floating-Point Unit (FPU) ........................................................................... 1-7 1.1.5 Memory Management Unit (MMU)................................................................ 1-7 1.1.6 Cache Unit ....................................................................................................... 1-8 1.1.7 Memory Unit.................................................................................................... 1-8 1.1.8 System Interface ............................................................................................ 1-10 1.2 Levels of the PowerPC Architecture.................................................................. 1-10 1.3 The 601 as a PowerPC Implementation............................................................. 1-11 1.3.1 Features.......................................................................................................... 1-12 1.3.2 Registers and Programming Model ............................................................... 1-13 1.3.2.1 PowerPC Registers and Programming Model ........................................... 1-13 1.3.2.1.1 General-Purpose Registers (GPRs)........................................................ 1-13 1.3.2.1.2 Floating-Point Registers (FPRs)............................................................ 1-14 1.3.2.1.3 Condition Register (CR)........................................................................ 1-14 1.3.2.1.4 Floating-Point Status and Control Register (FPSCR) ........................... 1-14 1.3.2.1.5 Machine State Register (MSR).............................................................. 1-14 Contents iii CONTENTS Paragraph Page Title Number Number 1.3.2.1.6 Segment Registers (SRs)........................................................................1-14 1.3.2.1.7 Special-Purpose Registers (SPRs)..........................................................1-14 1.3.2.1.8 User-Level SPRs ....................................................................................1-14 1.3.2.1.9 Supervisor-Level SPRs ..........................................................................1-15 1.3.2.2 Additional Registers in the 601..................................................................1-16 1.3.3 Instruction Set and Addressing Modes...........................................................1-18 1.3.3.1 PowerPC Instruction Set and Addressing Modes.......................................1-18 1.3.3.1.1 PowerPC Instruction Set ........................................................................1-18 1.3.3.1.2 Calculating Effective Addresses ............................................................1-19 1.3.3.2 601 Instruction Set......................................................................................1-20 1.3.4 Cache Implementation....................................................................................1-20 1.3.4.1 PowerPC Cache Characteristics .................................................................1-21 1.3.4.2 601 Cache Implementation.........................................................................1-21 1.3.5 Exception Model ............................................................................................1-22 1.3.5.1 PowerPC Exception Model ........................................................................1-23 1.3.5.2 The 601 Exception Model ..........................................................................1-24 1.3.6 Memory Management ....................................................................................1-27 1.3.6.1 PowerPC Memory Management ................................................................1-27 1.3.6.2 601 Memory Management .........................................................................1-28 1.3.7 601 Instruction Timing...................................................................................1-29 1.3.8 System Interface .............................................................................................1-31 1.3.8.1 Memory Accesses.......................................................................................1-32 1.3.8.2 I/O Controller Interface Operations ...........................................................1-33 1.3.8.3 601 Signals .................................................................................................1-33 1.3.8.4 Signal Configuration ..................................................................................1-34 1.3.8.5 Real-Time Clock ........................................................................................1-35 Chapter 2 Registers and Data Types 2.1 Normal Instruction Execution State .....................................................................2-1 2.1.1 Changing Privilege Levels ...............................................................................2-6 2.2 User-Level Registers ............................................................................................2-6 2.2.1 General Purpose Registers (GPRs)...................................................................2-6 2.2.2 Floating-Point Registers (FPRs).......................................................................2-7 2.2.3 Floating-Point Status and Control Register (FPSCR) ......................................2-8 2.2.4 Condition Register (CR).................................................................................2-11 2.2.4.1 Condition Register CR0 Field Definition...................................................2-12 2.2.4.2 Condition Register CR1 Field Definition...................................................2-12 2.2.4.3 Condition Register CRn Field—Compare Instruction...............................2-12 2.2.5 User-Level SPRs ............................................................................................2-13 2.2.5.1 MQ Register (MQ) .....................................................................................2-13 iv PowerPC 601 RISC Microprocessor User's Manual CONTENTS 2.2.5.2 Integer Exception Register (XER) .............................................................2-15 2.2.5.3 Real-Time Clock (RTC) Registers (User-Level) .......................................2-16 2.2.5.3.1 Real-Time Clock Lower (RTCL) Register ............................................2-17 2.2.5.3.2 Real-Time Clock Upper (RTCU) Register ............................................2-18 2.2.5.3.3 Reading the RTC....................................................................................2-18 2.2.5.3.4 RTC Synchronization in a Multiprocessor System................................2-19 2.2.5.4 Link Register (LR).....................................................................................2-19 2.2.5.5 Count Register (CTR) ................................................................................2-20 2.3 Supervisor-Level Registers ................................................................................2-20 2.3.1 Machine State Register (MSR) ......................................................................2-20 2.3.2 Segment Registers..........................................................................................2-22 2.3.3 Supervisor-Level SPRs ..................................................................................2-24 2.3.3.1 Synchronization for Supervisor-Level SPRs and Segment Registers........2-25 2.3.3.1.1 Context Synchronization........................................................................2-25 2.3.3.1.2 Other Synchronization Requirements by Register.................................2-29 2.3.3.2 DAE/Source Instruction Service Register (DSISR)...................................2-29 2.3.3.3 Data Address Register (DAR)....................................................................2-30 2.3.3.4