Jörg Fuhrmann A Digital Power Amplifier in 28 nm CMOS for LTE Applications FAU Studien aus der Elektrotechnik Band 6 Herausgeber der Reihe: Prof. Dr. Günter Roppenecker Jörg Fuhrmann A Digital Power Amplifier in 28 nm CMOS for LTE Applications Erlangen FAU University Press 2016 Bibliografische Information der Deutschen Nationalbibliothek: Die Deutsche Nationalbibliothek verzeichnet diese Publikation in der Deutschen Nationalbibliografie; detaillierte bibliografische Daten sind im Internet über http://dnb.d-nb.de abrufbar. Das Werk, einschließlich seiner Teile, ist urheberrechtlich geschützt. Die Rechte an allen Inhalten liegen bei ihren jeweiligen Autoren. Sie sind nutzbar unter der Creative Commons Lizenz BY-NC-ND. Der vollständige Inhalt des Buchs ist als PDF über den OPUS Server der Friedrich-Alexander-Universität Erlangen-Nürnberg abrufbar: https://opus4.kobv.de/opus4-fau/home Verlag und Auslieferung: FAU University Press, Universitätsstraße 4, 91054 Erlangen Druck: docupoint GmbH ISBN: 978-3-944057-94-1 (Druckausgabe) eISBN: 978-3-944057-95-8 (Online-Ausgabe) ISSN: 2363-8699 A Digital Power Amplifier in 28 nm CMOS for LTE Applications Ein digitaler Leistungsverstärker in 28 nm-CMOS für LTE-Anwendungen Der Technischen Fakultät der Friedrich-Alexander-Universität Erlangen-Nürnberg zur Erlangung des Doktorgrades DOKTOR-INGENIEUR vorgelegt von Jörg Fuhrmann aus Nürnberg Als Dissertation genehmigt von der Technischen Fakultät der Friedrich-Alexander-Universität Erlangen-Nürnberg Tag der mündlichen Prüfung: 25.04.2016 Vorsitzender des Promotionsorgans: Prof. Dr. rer.-nat. Peter Greil 1. Gutachter: Prof. Dr.-Ing. Dr.-Ing. habil. Robert Weigel 2. Gutachter: Prof. Dr. techn. Harald Pretl Acknowledgment First of all I thank Prof. Dr. techn. Harald Pretl for his guidance, con- structive discussions and his open door policy. He always found the time to support and listen to me, even in the most stressful phases of his own work. He constantly encouraged me and he paved the way for this work by setting up a great working environment and a good net- work inside the company. I deeply thank him and I could not imagine a better supervisor. I thank my Ph.D. colleague Patrick Oßmann for the constructive and good team work. I thank Krzysztof Dufrêne who started with us this work and who set a great foundation. I thank Moreira José whose con- structive support, especially during the hard phases of this project, was a key element to the success of the designs. I thank my office colleague Anas Saudi for the nice working environment that he created and for his unconditional support in the laboratory. I thank my managers Thomas Greifeneder and Volker Neubauer for their support and open door policy during the years. I thank Stephan Leuschner, Michael Fulde, Ofir Degani, Jonas Fritzin, Thomas Bauern- feind, Thomas Buggler, Jan Zaleski, Alexander Klinkan, Dirk Friedrich, Simon Grünberger, Daniel Gruber, Sven Hampel, Dejan Teodorovic, Alexander Huber and all other members of Danube Mobile Commu- nications Engineering (DMCE) and Intel® for their contributions to this work. I thank them for the nice working atmosphere and for all the extra hours and efforts they spent for discussions and support. I thank my professor Prof. Dr.-Ing. Dr.-Ing. habil. Robert Weigel for providing me the opportunity to do my Ph.D. thesis and for his guidance during the time. I also thank all the other colleagues of the Department for Electronics Engineering at the Friedrich-Alexander- Acknowledgment Universität Erlangen-Nürnberg for the friendly atmosphere on my oc- casional visits. I especially thank my parents Anton and Birgit Fuhrmann and my whole family, who constantly supported me during my whole life and who have always encouraged me to pursue my goals. I thank my girl- friend Amalia Lorca Ballestrín for her patience, support and under- standing during the last years. I was having a great time with her and she always gave me new strength to continue. I thank my friends for the nice moments we had during the rare free time while I was working on my thesis. I thank you all very much for your individual contributions and sup- port. The last years were a great and pleasant experience for me. I have enjoyed being with all of you and I hope that a lot of good years are following. - Jörg Fuhrmann Abstract The further development of the mobile communication standard to- wards the 4th generation (4G) long term evolution (LTE) and the simul- taneous development of technology standards create new challenges, that have to be fulfilled, while designing power amplifiers (PAs). The downscaling of complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) according to Moore’s law makes the overall transceiver system more compact and reduces the required chip area. Recently a fully integrated CMOS power amplifier was included in a single-chip 3rd generation (3G) high speed packet access (HSPA) trans- ceiver with a radio frequency digital to analog converter (RFDAC). For further integration the RFDAC and PA can be merged to a digital PA (DPA). The signal can be generated using polar modulation (PM) which allows a separated consideration of amplitude and phase. The current summing digital power amplifier (CSDPA) is one solution for fully in- tegrated CMOS PM architectures. A CSDPA can be implemented as switched power amplifier architecture with an inverse class-D PA that can theoretically achieve high efficiency what makes it a promising can- didate for fully integrated circuits. To proof the capability of 28 nm CMOS technology to provide watt- level output power a linear class-AB PA is designed. A DPA is imple- mented to further merge the design and additionally to be able of test- ing more advanced designs. Both designs are implemented in a front- end-of-line (FEOL) 28 nm CMOS technology. The designs use 7 copper layers and 1 aluminum layer as back-end-of-line (BEOL). The fully in- tegrated circuits include on-chip matching, biasing and electrostatic discharge (ESD) protection. To overcome the voltage stress for a single transistor the designs are implemented as a triple stack with feedback path from the drain of the upper transistor to the gate. This reduces the voltage stress of the transistor and increases the reliability. i Abstract The circuits are measured, by using sinusoidal signals, to determine the output power and efficiency. For linearity characterization the stan- dard of the 3rd generation partnership project (3GPP) is taken. Uni- versal terrestrial radio access (UTRA), evolved UTRA (E-UTRA) adja- cent power leakage ratio (ACLR) and error vector magnitude (EVM) are tested using LTE physical uplink shared channel (PUSCH) orthogonal frequency-division multiplexing (OFDM) quadrature phase-shift key- ing (QPSK)/16 quadrature amplitude modulation (16-QAM) test sig- nals with 1.4-20 MHz bandwidth (BW) at the required channel power (CHP). The linear stand-alone PA is designed for LTE frequency division du- plex (FDD) band 1. The bare bumped die measures 1:88 × 0:51 mm2 and is directly soldered on the printed circuit board (PCB). At pulsed measurements a maximum power-added efficiency (PAE) of 35.2 %, a drain efficiency ηd of 39.5 %, a gain of 15.5 dB and a maximum output power Pmax of 31.7 dBm are achieved at 1.83 GHz with 3.2 V supply volt- age. The use of digital predistortion (DPD) is shown in the frequency spectrum of a full allocated LTE signal with 15 MHz bandwidth (LTE-15) band 1 PUSCH 16-QAM OFDM signal. LTE requirements for the BWs 1.4-20 MHz are measured with full allocation of band 1 PUSCH QPSK signals. The required EVM of 17.5 %, UTRA ACLR of -33 dBc and E- UTRA of -30 dBc are fulfilled with the use of DPD for all BWs. The monolithic fully integrated DPA, implemented in a single-chip LTE transceiver system, was designed for LTE FDD band 7 and LTE time division duplex (TDD) bands 38, 40 and 41. The implementation has been optimized for operating in the 2.3-2.7 GHz range. It is imple- mented as digital polar transmitter (DPT) that is directly connected to the digital front end (DFE). The DFE converts the IQ modulated signal data to a polar modulated signal. The modulated phase information is contained in the local oscillator (LO) signal. The amplitude infor- mation is decoded by a segmented 15 bit field. The most significant bits (MSBs) are thermometer decoded to assure monotonicity. The 5 least significant bits (LSBs) are realized as binary weighted cells to reduce complexity. The signal’s amplitude and phase information is combined again inside the DPA. It already provides the required LTE output power without further amplification. The output of the DPA is matched by a transformer. The transformer also acts as a balun and ii Abstract transforms the differential signal into a single-ended one. By using an inverse class-D PA design for the unit cells (UCs) in the cell field, their outputs can be shorted and connected to an output matching network (OMN). This results in a compact implementation. The inductive el- ement of the matching network is merged into the OMN. The trans- former is divided into one on-chip winding and a secondary winding in the package. Since the secondary winding of the transformer is re- alized in an extra redistribution layer (RDL) inside the package the on- chip metal copper lines can be used for the primary windings. The primary winding is implemented in the thickest metal layer and in the aluminum layer to ensure good conductivity and decreased insertion losses. This results in an improved quality factor of the OMN. The output of the transformer is connected to a 50 Ω output load at the PCB. The center tap of the transformer is connected to the 2.5 V power supply.