Serial Interfaces – Part 2 ECE 153B Sensor & Peripheral Interface Design Winter 2016 The I2C Bus I2C (Inter Integrated Circuit) Bus Serial, 2-wire bus Different than point–to–point communications Developed by Philips (now NXP) Semiconductor in early 1980’s Intel SMBus (System Management Bus) is a subset of I2C Software controlled addressing No address decoding hardware Available as a built-in peripheral on many μControllers and μProcessors Winter 2016 ECE 153B - Sensor & Peripheral Interface 2 Design - Serial Interfaces - Part 2 The I2C Bus Revision / Speed History The original (1982) 100-kHz I²C system was created as a simple internal bus system for building control electronics with various Philips chips Version 1 (1992) added 400-kHz Fast-mode (Fm) and a 10-bit addressing mode to increase capacity to 1008 nodes This was the first standardized version Version 2 (1998) added 3.4-MHz High-speed mode (Hs) with power- saving requirements for electric voltage and current Version 3 (2007) added 1-MHz Fast-mode plus (Fm+), and a device ID mechanism Version 4 (2012) added 5-MHz Ultra Fast-mode (UFm) for new USDA and USCL lines using push-pull logic without pull-up resistors, and added assigned manufacturer ID table Winter 2016 ECE 153B - Sensor & Peripheral Interface 3 Design - Serial Interfaces - Part 2 The I2C Bus 2 Wire, Serial Bus SDA – Serial Data SCL – Serial Clock Many masters, many slaves possible always at least one master (µcontroller or DSP) Winter 2016 ECE 153B - Sensor & Peripheral Interface 4 Design - Serial Interfaces - Part 2 The I2C Bus Electrical implementation Open drain (collector) connection to data and clock buses Winter 2016 ECE 153B - Sensor & Peripheral Interface 5 Design - Serial Interfaces - Part 2 The I2C Bus Each device has a unique 7-bit I2C address 4 most significant bits are typically fixed and assigned to specific categories of devices e.g. 4’b1010 is assigned to serial EEPROMs 3 less significant bits are programmable, often through hardware address pins Winter 2016 ECE 153B - Sensor & Peripheral Interface 6 Design - Serial Interfaces - Part 2 I2C Bus Terminology Master The component that initiates a transfer (Start command), generates the clock signal (SCL), and terminates the transfer (Stop command) Slave The device addressed by the master A slave can be either receiver or transmitter Transmitter Device that sends data to the bus can be master-transmitter or slave-transmitter Receiver Device that receives data from the bus can be master-receiver or slave-receiver Winter 2016 ECE 153B - Sensor & Peripheral Interface 7 Design - Serial Interfaces - Part 2 I2C Bus – Terminology Illustrated Master always drives the clock line which sets the timing for all transactions Master can be either transmitter or receiver, depending on data direction Winter 2016 ECE 153B - Sensor & Peripheral Interface 8 Design - Serial Interfaces - Part 2 More I2C Bus Terminology Multi-master The ability for more than one master to co-exist on the bus at the same time without collision or data loss. Obviously, though multiple masters may be present, only one can be master in any one transaction Arbitration The prearranged procedure that authorizes only one master at a time to take control of the bus Synchronization The prearranged procedure that synchronizes the clock signals provided by two or more masters. Winter 2016 ECE 153B - Sensor & Peripheral Interface 9 Design - Serial Interfaces - Part 2 The I2C Bus Nomenclature for I2C Bus Transfer Conditions and States F (FREE) The bus is free or idle; the data line SDA and the SCL clock are both in the high state S (START) or R (RESTART) Data transfer begins with a Start condition. The level of the SDA data line changes from high to low, while the SCL clock line remains high. When this occurs, the bus becomes 'busy‘ C (CHANGE) While the SCL clock line is low, the data bit to be transferred can be applied to the SDA data line by a transmitter. During this time, SDA may change its state, as long as the SCL line remains low. Winter 2016 ECE 153B - Sensor & Peripheral Interface 10 Design - Serial Interfaces - Part 2 The I2C Bus More nomenclature for I2C Bus Transfer Conditions and States D (DATA) A high or low bit of information on the SDA data line is valid during the high level of the SCL clock line This level must be kept stable during the entire time that the clock remains high to avoid misinterpretation as a Start or Stop condition P (STOP) Data transfer is terminated by a Stop condition This occurs when the level on the SDA data line passes from the low state to the high state, while the SCL clock line remains high When the data transfer has been terminated, the bus is free once again Winter 2016 ECE 153B - Sensor & Peripheral Interface 11 Design - Serial Interfaces - Part 2 I2C Bus Transactions I2C address of the targeted device is sent in the first byte after Start condition LSB of initial byte indicates direction of transfer (R/W) Each transmission sequence begins with Start condition and ends with Stop or ReStart condition After every 8 data bits in one direction, an "acknowledge" bit is transmitted in the other direction The transmitter and receiver switch roles for one bit and the erstwhile receiver transmits a single 0 bit (ACK) back Winter 2016 ECE 153B - Sensor & Peripheral Interface 12 Design - Serial Interfaces - Part 2 I2C Bus Transactions If the transmitter sees a 1 bit (NACK) instead, it learns that: (If master transmitting to slave) The slave is unable to accept the data. No such slave, command not understood, or unable to accept any more data (If slave transmitting to master) The master wishes the transfer to stop after this data byte Winter 2016 ECE 153B - Sensor & Peripheral Interface 13 Design - Serial Interfaces - Part 2 I2C Bus Transactions Data transfer is initiated with the START bit (S) when SDA is pulled low while SCL stays high Then, SDA sets the transferred bit while SCL is low (blue) and the data is sampled (received) when SCL rises (green) When the transfer is complete, a STOP bit (P) is sent by releasing the data line to allow it to be pulled up while SCL is constantly high In order to avoid false marker detection, the level on SDA is changed on the falling edge and is captured on the rising edge of SCL Winter 2016 ECE 153B - Sensor & Peripheral Interface 14 Design - Serial Interfaces - Part 2 SPI – Serial Peripheral Interface Developed by Motorola Also known as Serial Synchronous Interface (SSI) 3- or 4-wire serial interface Optional 4-wire (SS=slave select) is not bussed Full-duplex data transfer Winter 2016 ECE 153B - Sensor & Peripheral Interface 15 Design - Serial Interfaces - Part 2 SPI – Serial Peripheral Interface No special protocol Just a simple shift register MSB generally transmitted first All data transfers are full-duplex Data are transferred even if they have no meaning Winter 2016 ECE 153B - Sensor & Peripheral Interface 16 Design - Serial Interfaces - Part 2 SPI – Serial Peripheral Interface Flexible clocking strategies Clock is not free-running like I2C Synchronizes after each transfer Programmable clock phase (CPHA) and polarity (CPOL) established by master Clock speed can be quite Red line indicates CPHA =0 high Blue line indicates CPHA = 1 e.g. an adaptation for SD cards uses 25MHz Winter 2016 ECE 153B - Sensor & Peripheral Interface 17 Design - Serial Interfaces - Part 2 SPI – Serial Peripheral Interface Two possibilities for connecting multiple slaves Star (slaves in parallel) Slaves in Series Note: SS may Note: extra not be SS signals needed Winter 2016 ECE 153B - Sensor & Peripheral Interface 18 Design - Serial Interfaces - Part 2 USB The Universal Serial Bus Winter 2016 ECE 153B - Sensor & Peripheral Interface 19 Design - Serial Interfaces - Part 2 USB Developed (1996) to provide simple connectivity between PC’s and a diverse range of peripheral devices Original consortium included Intel, Compaq, Microsoft, NEC, Digital Equipment Corporation, IBM, Nortel USB is both a serial protocol and a physical link One pair of wires transmits differential data Second pair of wires provides power to downstream peripherals Up to 127 USB devices can be connected to a host computer port Winter 2016 ECE 153B - Sensor & Peripheral Interface 20 Design - Serial Interfaces - Part 2 USB Data rates USB-1.1 (1996) 1.5 Mbps (low speed) and 12 Mbps (full speed) USB-2.0 (2000) 480 Mbps (Hi-Speed) . Compare that with I2C: 100 Kbps up to 3.4 Mbps max USB-3.0 (2008) Up to 5Gbps (SuperSpeed) Uses different connectors, downward compatible Winter 2016 ECE 153B - Sensor & Peripheral Interface 21 Design - Serial Interfaces - Part 2 USB Peripherals can be connected and removed without powering the entire system down Referred to as “hot swapping” Peripheral power (for the interface) is provided through the USB connection USB peripherals are slaves, responding to commands from the host When a peripheral is attached to a USB network, the host communicates with the device to learn its identity and to discover which device driver is required Process is called “bus enumeration” This is what takes so long whenever you plug or unplug Winter 2016 ECE 153B - Sensor & Peripheral Interface 22 Design - Serial Interfaces - Part 2 USB USB peripherals only communicate with the host Peripherals cannot communicate directly with each other USB communications take place between the host and “endpoints” located in the peripherals All USB transfers occur through “virtual pipes” When establishing communications with the peripheral, each endpoint returns a descriptor A data structure that tells the host about the endpoint’s configuration and its expectations Descriptors include: . transfer type . maximum size of packets . optionally the interval for data transfers and the required bandwidth .