Wireless Information Transmission System Lab. EDA Tools, Failure Analysis Tools and Reliability Testing for System IC Development Hung-Chih Chiang Institute of Communications Engineering National Sun Yat-sen University EDA Markets 6,000 PCB Design 單 位 5,000 IC CAD ： CAE/Misc. 百 CAE/Gate Level 萬 4,000 美 CAE/RTL 元 CAE/ESL 3,000 2,000 1,000 0 2000 2001 2002 2003(e) 2004(e) 2005(f) 2006(f) 2007(f) 資料來源：工研院IEK (2004/04) 2 Outline EDA Tools and Design Flow System Level Simulation Tools Front-end IC Design Flow and Design Tools Back-end IC Design Flow and Design Tools System Verification Tools Failure Analysis Tools Reliability Testing 3 System Level Simulation Purpose: Ö Algorithm verification Ö Protocol design verification Ö System Integrity verification 4 System Level Simulation Tools C, C++: SystemC: Ö A modeling platform supports different levels of abstraction. Ö A simulation kernel. Matlab: SPW: 5 Cell-Base Front–END Design Flow Front-End IC Design Flow Design Specification RTL Design and Simulation RTL Verilog Library File Code .v or .V Logic Synthsis Constraint file static timing anaysis / design rules check Front_End Pre_sim SDF file change_names / Pre_sim Verilog write_timing (SDF) gate-level netlist code.vg or .VG Pre_sim EDIF Pre-layout Gate Level Simulation netlist GTL Verilog 1st Sign-Off Code Floorplan, Placement .vg or .VG and Route 6 RTL Simulation Tools Verilog-XL (Cadence) : a standard sign off simulator. NCVerilog (Cadence) : a compiled simulator, works as fast as VCS, and still maintains the sign off capabilities of Verilog-XL. This simulator is good when it comes to gate level simulations. VCS (Synopsis) : a compiled simulator like NCverilog. This simulator is faster when it comes to RTL simulation. Few more things about this simulator are direct C kernel interface, Covermeter code coverage embedded, better integration with VERA and other Synopsys tools. Finsim (Fintronic) : This is 100% compatible simulator with Verilog-XL, runs on Linux, Windows and Solaris. This is compiled simulator like VCS and NCVerilog, but slower then VCS and NCVerilog. Modelsim (Model Technology): popular and cheap simulator, has got good debugging capabilities, and nice GUI. This simulator can be used for block level design and verification. But sign-off should not be done with this simulator. Polaris (Avanti) : Cycle based simulator. Smash (Dolphin) : mixed signal, Verilog, VHDl simulator 7 Debugging Tools Debussy (SprintSoft) : Ö a powerful debugging tool with a nice GUI. Modelsim (Model Technology): Ö popular and has a nice GUI. 8 Logic Synthesis Tools Design Complier (Synopsys) : Ö the most popular logic synthesizer, bottom-up approach Ambit (Cadence): Ö a fast logic synthesizer, top-down approach 9 Synthesis Methodology Compile Strategies Ö Bottom-up – Synopsys Design Complier Traditional method used in building up hierarchy Each module is individually synthesized Uses manual time budgets or a default budget May not produce optimal design Prone to error in manually specified time budgets Ö Hierarchical (Top-down) – Cadence Ambit Build hierarchical design objects with constraints applied at the top-most level Entire design hierarchy is optimized together Only top level time budgets are required Requires fewer files and produces more optimal design than with bottom-up approach 10 Bottom-Up synthesis Approach Always specify at least a default time budget! Time budgets are easiest with registered outputs (Ambit) set_input_delay 2 –clock clk [find –port –input *] set_external_delay 2 –clock clk [find –port –output *] Q Q Q Q + Q 11 Hierarchical Synthesis Approach Hierarchical synthesis avoids inter-module time budgeting An entire design hierarchy is optimized together Sub-designs are optimized in full context of top of hierarchy Only top level time budgets are required (Ambit) do_xform_optimize_slack -time_budget do_optimize -time_budget Top bottom1 bottom2 Q Q 12 SoC Synthesis Recommend a bottom-up approach. Ö Each IP/macro should have its own synthesis script to ensure the right internal timing. Chip-level Synthesis Ö Consist only connecting the macros and resizing the output drive buffers. 13 Partitioning The top-levels of design hierarchy should be interconnect only I/O PAD Asynchronous Logic 20K 20K BIST Clock Generation/ Embeded Core PLL UP 40K 40K Test Module 100K RAM JTAG 14 Layout Design Flow Overview Hierarchical Multi-million gate APR and gate level floorplan. Timing Driven/Power Driven/CTS (Clock Tree Synthesis) APR. Signal integrity(antenna/cross talk/voltage drop/electron-migration) violation analysis and removal. SOC integration. LVS/DRC/ERC physical verification. Scan chain re-ordering service Advanced 3D RC extraction (Gate Level and Transistor Level) SDF generate and skew report ECO/LVL 15 Clock Tree Insertion 16 Cell-Base Back-End Design Flow Cell-Base Back-End IC Design Flow Pre-layout Gate Level Simulation GTL Verilog Code .vg or .VG Cell Library Tech File Floorplan Labrary Mapping File Placement and Route Netlist File post-layout timing analysis / design rule check Back_End Phsical Verification LVS APR SDF Out 17 Cell-Base Back-End Design Flow Post APR Not O.K Gate Level O.K Simulation No (Avanti Flow) Logic Synthsis Optimization Milkyway2Star ? Load SDF and Netlist File Yes Layer GRD APR ECO Milkyway2Star GDS II Out Mapping File File APR SDF Out SDF Out DRC/ERC/ Run Set File LVS Res TCAD File Yes SDF Out ? GRD File Skip Cell File Post Layout O.K No Gate Level Simulation Star-RC Tech 2nd Sign-Off File Not O.K Runset File Logic Synthsis Star-DC Tech Optimization File Load SDF and Netlist File pio File APR ECO APR SDF Out Tape Out GDS II File 18 APR Silicon Ensemble (Cadence) : Ö good for interface with Cadence synthesizer. Apollo (Avanti/Synopsis): Ö used to be the most popular APR tool. Astro (Synopsis): Ö new version of Apollo. 19 RC Extraction Hyper Extract (Cadence) : Star-RC (Avanti/Synopsys): Ö a popular RC extraction tool 20 Layout Verification (DRC/ERC/LVS) Herculus (Avanti/Synopsys) : Dracula (Cadence): 21 Layout Editor Virtuoso (Cadence): Laker (SprintSoft): Ö on-line rule driven & point to point routing Tanner (Mentor Graphics): Enterprise (Synopsys): 22 Transistor Level Verification HSpice (Avanti/Synopsys): Ö accurate but slow. Star-Sim: Ö Fast but not as accurate as HSpice. P-Spice: Ö for PC users. 23 Circuit Simulation Conditions Operation Temperature Ö Low (-55°C~0°C) Ö Typical (25°C) Ö High(80°C~120°C) Spice Model Ö FF/TT/SS/FS/SF 24 System Verification Requirements: Ö Mixed level, mixed-language, mixed-signal simulation and debugging Ö Abundant IP libraries and models 25 System Verification Tools CoCentric System Studio (Synopsys): Virtual Component Co-design/Incisive Function Verification Platform (Cadence): 26 Outline EDA Tools and Design Flow System Level Simulation Tools Front-end IC Design Flow and Design Tools Back-end IC Design Flow and Design Tools System Verification Tools Failure Analysis Tools Reliability Testing 27 Failure Analysis Tools FIB (Focused Iron Beam) Laser EMMI (EMission MIcroscope) Probe Station E-Beam X-Ray, SAM (Scanning Acoustic Microscope) 28 FIB Flow 29 EMMI Example: Leakage 30 E-Beam Example: 31 X-Ray Example: 32 Outline EDA Tools and Design Flow System Level Simulation Tools Front-end IC Design Flow and Design Tools Back-end IC Design Flow and Design Tools System Verification Tools Failure Analysis Tools Reliability Testing 33 Reliability Testing (1) ESD (ElectroStatic Discharge) Ö Human-Body Mode Ö Machine Mode Ö Charged-Device Mode Latch Up Ö Parasitic transistors 34 Reliability Testing (2) High/Low Temperature Operating Life Temperature & Humidity with Bias High Accelerated Stress Pressure Cooker Thermal Shock Temperature Cycling High/Low Temperature Storage Temperature & Humidity Storage Temperature & Humidity Cycling Solderability 35 Summaries Following a complete design flow increases the chance of first cut work. Failure analysis tools help to resolve problems of ICs. Reliability tests provide quality assurance of products. 36.